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AssigneeHitachi, Ltd.
InventorsKoichiro Ishibashi, Shuji Ikeda, Harumi Wakimoto, Kenichi Kuroda
Estimating the term…
The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
A semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
A semiconductor integrated circuit device, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
Inorganic electric semiconductor devices
Term end not estimated
1. Field Of The Invention
The present invention relates to a semiconductor integrated circuit. More particularly, it is suitable for a CMOS semiconductor integrated circuit suited to implement a high-speed operation with a low electric power. In particular, it relates to a semiconductor integrated circuit which can be implemented with a small area and without increasing the number of photomasks.
2. Description Of The Prior Art
FIGS. 1A-1D are configuration diagrams of a first embodiment in the present invention;
FIGS. 2A-2D are configuration diagrams for comparing the conventional invention with the present invention;
FIGS. 3A-3H are cross sectional views for illustrating a fabricating process in the present invention;
Referring to the accompanying drawings, the explanation will be given below concerning embodiments of the present invention.
FIGS. 1A-1D illustrate a first embodiment of the present invention. FIGS. 1A-1D are a logic diagram of an inverter circuit which is a basic circuit of a CMOS, a circuit diagram thereof, a layout diagram thereof and a cross sectional view thereof, respectively. In the logic diagram shown in FIG. 1A, reference numerals 11 and 12 denote an input terminal and an output terminal, respectively. In the circuit diagram shown in FIG. 1B, reference numeral 13 denotes a PMOS transistor, 14 an NMOS transistor, 15 a diode, 16 a line for a substrate of the PMOS transistor, 17 a power line, 19 a line for a substrate of the NMOS transistor, and 18 a ground line.
As illustrated in FIGS. 1A-1D, the present embodiment relates to the following CMOS integrated circuit. The electric potentials of the substrates of the transistors are connected through the lines 16 and 19. The electric potentials of the lines are controlled so as to set the threshold voltages of the MOS transistors to be the desired values, thereby making it possible to implement the low-power and high-speed operation. Also, the diode 15 is inserted in order to prevent a phenomenon that, in an integrated circuit fabricating process such as etching, the gate electrodes of the MOS transistors 13 and 14 are charged and thus the oxide films are broken down.