Method of stress and damage elimination during formation of isolation device

#1. Field of the Invention

#The invention relates to a method of stress and damage elimination during the formation of isolation device, and more particularly to a method of stress and damage elimination during the formation of shallow trench isolation. The stress and damage elimination can prevent semiconductor devices from reliability degradation.

#2. Description of the Prior Art

#A better understanding of the invention may be derived by reading the following detailed description with reference to the accompanying drawing wherein:

#FIGS. 1A-1D are a series of cross-sectional schematic diagrams illustrating the formation of the shallow trench isolation in accordance with the prior art; and

#FIGS.2A-2D are a series of cross-sectional schematic diagrams illustrating the treatment of the trench structure in accordance with the present invention.

#The semiconductor devices of the present invention are applicable to a board range of semiconductor devices and can be fabricated from a variety of semiconductor materials. While the invention is described in terms of a single preferred embodiment, those skilled in the art will recognize that many steps described below can be altered without departing from the spirit and scope of the invention.

#Furthermore, there is shown a representative portion of a semiconductor structure of the present invention in enlarged, cross-sections of the two dimensional views at several stages of fabrication. The drawings are not necessarily to scale, as the thickness of the various layers are shown for clarify of illustration and should not be interpreted in a limiting sense. Accordingly, these regions will have dimensions, including length, width and depth, when fabricated in an actual device.

#In the present invention, a method of preventing reliability degradation a semiconductor device during formation of a trench isolation device is provided. The method comprises providing a semiconductor substrate and a pad oxide layer is first formed on the semiconductor substrate. A dielectric layer, such as a silicon nitride layer, is formed on the pad oxide layer. A photo-resist layer is formed on the dielectric layer, which exposes a portion of the dielectric layer where a trench structure is formed. The portion of the dielectric layer and the pad oxide layer is removed to expose the portion of the semiconductor substrate. Then the exposed semiconductor substrate is etched to form the trench structure. The trench structure is then subjected to annealing whereby prevents the semiconductor device from reliability degradation. It is also applied on forming a side-wall oxide layer at a side-wall of the trench structure and then subjecting the side-wall oxide layer to annealing whereby eliminates oxidation-induced stress of the trench structure.