Copper polish slurry for reduced interlayer dielectric erosion and method of using same
AssigneeIntel Corporation
InventorAnne E. Miller
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AssigneeIntel Corporation
InventorAnne E. Miller
Estimating the term…
Slurries for use in the chemical mechanical polishing (CMP) of copper and copper diffusion barriers that reduce pattern sensitive erosion of an underlying dielectric layer include at least one surfactant. Inclusion of surfactants, such as cetyltrimethylammonium bromide in a slurry mixture can reduce pattern sensitive erosion of dielectric materials such as silicon oxide, and fluorinated oxides of silicon that would otherwise occur during CMP of copper and copper diffusion barriers as is typical in the formation of copper interconnect lines in integrated circuits.
A slurry, comprising a mixture of:
A copper polish slurry, comprising in combination:
A method of making a slurry for the chemical mechanical polishing of copper and copper diffusion barriers, comprising:
A method of polishing copper, comprising:
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1. Field of the Invention
The invention relates generally to the manufacture of integrated circuits, and more particularly to slurries for use in chemical mechanical polishing of copper, copper alloys, and copper diffusion barriers in the formation of interconnect lines on integrated circuits.
2. Background
FIG. 1 is a schematic cross section of a portion of a wafer showing erosion of the ILD layer as a result of conventional CMP.
FIG. 2 is a bar graph showing the relative effectiveness of various surfactants on reducing pattern sensitive erosion.
FIG. 3 is a bar graph showing the relative removal rates of Cu and ILD using slurries with and without a surfactant additive.
Overview
Copper interconnect lines on integrated circuits are typically formed by damascene metallization processing which includes removal of excess copper and copper barrier layers by way of CMP. When CMP is performed with conventional slurries, pattern sensitive erosion is observed in areas of the integrated circuit having high interconnect density. FIG. 1 illustrates the problem of increased levels of erosion in the high density interconnect areas. As shown in FIG. 1, an interlayer dielectric (ILD) 102, has trenches lined with a copper diffusion barrier 104, and further has copper metal 106 overlying the diffusion barriers 104, and essentially filling the trenches. A polishing pad 110, together with a plurality of slurry particles 108 are shown to illustrate the polishing process which produces erosion 112. Pattern sensitive erosion produces greater levels of erosion in areas where the ratio of metal to dielectric is high, than in areas of the integrated circuit where interconnect lines are relatively sparse, and therefore the width of the interlayer dielectric, i.e., the space between interconnect lines is greater.
One approach to solving this problem for integrated circuits which use Ta as the Cu diffusion barrier involves a two-step polishing process and the use of slurry having a high selectivity to Ta. However, the thickness of the barrier layer is not sufficient to protect the dense structure from erosion. It is also desirable to polish the copper and barrier layer as a one-step operation. Attempts to solve either of these problems by simply creating a slurry with a high ILD selectivity (e.g., <10 angstroms per min SiO2 removal rate) have not improved dishing or erosion issues.