Shallow trench isolation planarized by wet etchback and chemical mechanical polishing

#1. Field of the Invention

#The present invention relates generally to methods for forming aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications. More particularly, he present invention relates to methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.

#2. Description of the Related Art

#The objects, features, and advantages of the present invention are understood within the context of the Description of the Preferred Embodiments, as set forth below. The Description of the Preferred Embodiments is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:

#FIG. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 show a series of schematic cross-sectional diagrams illustrating the results of forming in accord with a general embodiment of the method of the present invention which comprises a first preferred embodiment of the present invention a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer within a microelectronics fabrication.

#FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. 11 show a series of schematic cross-sectional diagrams illustrating the results of forming in accord with a more specific embodiment of the present invention which comprises a second preferred embodiment of the present invention a series of trench isolation fill layers within a series of isolation trenches within a semiconductor substrate employed within a semiconductor integrated circuit microelectronics fabrication.

#The present invention provides a high-density plasma chemical vapor deposition (HDP-CVD) method in conjunction with chemical mechanical polish (CMP) planarizing method for forming within a microelectronics fabrication a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate comprising a series of mesas of substantially equivalent heights but differing widths, where the series of patterned planarized aperture fill layers is formed with optimal uniformity and planarity. The present invention realizes the foregoing objects by employing interposed between the high-density plasma chemical vapor deposition (HDP-CVD) method and the chemical mechanical polish (CMP) planarizing method an etch back method which is applied to a blanket fill aperture layer from which is formed the patterned aperture fill layers. The blanket aperture fill layer, which is originally formed employing a high-density plasma chemical vapor deposition (HDP-CVD) method to a thickness at least equal to the height of the mesas, is etched back to a thickness within each aperture less than the height of the mesas. When etched back in such a fashion, a series of blanket aperture fill layer protrusions residues formed upon the mesas may be removed by employing chemical mechanical polish (CMP) planarizing method while providing the series of patterned planarized aperture fill layers of optimal uniformity and planarity. Although the method of the present invention provides value when forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications, the method the present invention may also be employed within microelectronics fabrications including but not limited to semiconductor integrated circuit microelectronics fabrications, solar cell microelectronics fabrications ceramic substrate microelectronics fabrications, and flat panel display microelectronics fabrications to form therein patterned planarized aperture fill layers including but not limited to patterned planarized aperture fill conductor layers, patterned planarized semiconductor aperture fill layers and patterned planarized aperture fill dielectric layers with similarly optimal uniformity and planarity with topographic substrate layers including but not limited to topographic conductor substrate layers, topographic semiconductor substrate layers, topographic dielectric substrate layers and composites thereof.

#Referring now to FIG. 1, there is shown a series of schematic cross-sectional diagrams illustrating the results of forming within a microelectronics fabrication in accord with a general embodiment of the present invention which comprises a first preferred embodiment of the present invention a series of patterned planarized aperture fill layers within topographic substrate layer defined by a series of mesas of substantially equivalent height but differing widths, where the series of patterned planarized aperture fill layers is formed employing a high density plasma chemical vapor deposition (HDP-CVD) method and a subsequent partial removal by blanket etching back of a portion of the surface of the aperture fill layer, followed by chemical mechanical polish (CMP) planarizing method. Shown in FIG. 1 is a schematic cross-sectional diagram of the microelectronics fabrication at an early stage in its fabrication in accord with the method of the present invention. A topographic substrate layer 10 defined by a series of narrow mesas 11a, 11b and 11c of width W1 having interposed therebetween a pair of narrow apertures 13a and 13b of width W2, where the series of narrow apertures 13a and 13b are separated from a wide mesa 11d of width W4 by a wide aperture 13c of width W3. Within he first preferred embodiment of the method of the present invention, the topographic substrate layer 10 may be employed within a microelectronics fabrication selected from the group including but not limited to semiconductor integrated circuit microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications, and flat panel microelectronics fabrications. Although not specifically illustrated within the schematic cross-sectional diagram of FIG. 1, the topographic substrate layer 10 may be formed from the substrate alone employed within the microelectronics fabrication, or in the alternative, the topographic substrate layer 10 may be formed employing a composite of a substantially flat substrate employed within the microelectronics fabrication, upon which substantially flat substrate is formed an additional patterned layer to form in the aggregate the topographic substrate layer 10. Within the first preferred embodiment of the method of the present invention, the substrate alone, whether by itself substantially flat or by itself to topographic substrate layer, in conjunction with the patterned layer, may each be formed independently of materials including microelectronics conductor materials, microelectronics semiconductor materials, microelectronics dielectric materials and composites thereof.

#Referring still to FIG. 1, within the first preferred embodiment of the present invention the width W1 of each narrow mesa 11a, 11b and 11c within the series of narrow mesas is typically and preferably between about 0.25 and 0.5 microns. Similarly, within the first preferred embodiment of the present invention the width W2 of each narrow aperture 13a or 13b within the pair of narrow apertures is typically and preferably from about 0.25 to about 0.5 microns. Yet similarly, within the first preferred embodiment of the present invention, the width W3 of the wide aperture 3c is typically and preferably wider than about 3 microns. Still yet similarly, within he first preferred embodiment of the present invention, the width W4 of the wide mesa 11d is typically and preferably wider than about 3 microns. Finally, within the first preferred embodiment of the present invention, each of the mesas 11a, 11b and 11c preferably has a substantially equivalent height H, as illustrated in FIG. 1, of from about 5000 to about 7000 angstroms, where the term “substantially” is intended to accommodate localized differences in microelectronics fabrication methods employed when forming the series of mesas 11a, 11b and 11c using conventional photolithographic and chemical processes.