Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device including a non-volatile memory device and a resistance element including a resistance conductive layer, the method comprising the steps of:

• forming a first dielectric layer above a semiconductor layer;
• forming a first conductive layer above the first dielectric layer;
• forming a stopper layer above the first conductive layer;
• patterning the stopper layer and the first conductive layer to form a gate layer and the resistance conductive layer;
• forming sidewall control gates through an ONO film on both side surfaces of the gate layer;
• removing the stopper layer formed above the resistance conductive layer;
• forming a second dielectric layer above at least the resistance conductive layer;
• forming a third dielectric layer above the gate layer and the resistance conductive layer;
• polishing the third dielectric layer such that the stopper layer is exposed, and the second dielectric layer formed above the resistance conductive layer remains;
• removing the stopper layer;
• forming a second conductive layer above the gate layer and the resistance conductive layer;
• patterning the second conductive layer to form a word line;
• and
• patterning the gate layer to form a word gate.

A method for manufacturing a semiconductor device including a non-volatile memory device and a resistance element including a resistance conductive layer, the method comprising the steps of:

• pattering a stopper layer and a first conductive layer to form a gate layer;
• patterning the stopper layer, a dielectric layer and the first conductive layer to form a resistance conductive layer;
• forming sidewall control gates on both side surfaces of the gate layer through ONO films at least within a memory region of the semiconductor device;
• forming a second conductive layer above the gate layer and the resistance conductive layer;
• forming a word line by patterning the second conductive layer;
• and
• forming a word gate by patterning the gate layer.