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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBor-Cheng Chen, Yu-Feng Tai
Estimating the term…
A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET's.
A method of forming a plasma-damage testing structure comprising:
A method of detecting plasma damage comprising:
A method of detecting plasma damage comprising:
A plasma-damage testing structure comprising:
Dependencies are inferred from the claim text.
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Structural arrangements therefor: circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or…
Generic processes or apparatus for the manufacture or treatment of devices covered
Term end not estimated
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of early detection of plasma/charging damage in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
In the accompanying drawings forming a material part of this description, there is shown:
FIG. 1 is a top-view representation of a testing structure of the prior art.
FIG. 2 is a representation of the difference in sensitivity of a prior art testing structure and the testing structure of the present invention.
Referring now to FIG. 1, there is illustrated a conventional plasma-damage testing structure of the prior art. Active area 10 is shown. Field oxide area 12 has been formed over the semiconductor substrate in the active area. Polysilicon gate 16 is shown within the active area. The gate oxide layer, not shown, underlies and is covered by the polysilicon gate 16.
FIG. 2 illustrates the degree of plasma-induced damage to the gate oxide shown across the top of the figure where no damage occurs to the left of line 22. Increasing damage is shown to the right of line 22 in the direction of the arrow 24. Slight damage occurs immediately to the right of line 22. With a testing structure of the prior art, such as that shown in FIG. 1, there is a large “blind spot” 26 where damage occurs, but is not revealed by the testing structure. Greater damage to the right of the blind spot 26 can be caught by the testing structure.
In contrast, with the testing structure of the present invention, there is only a small blind spot 28. Damage to the right of the blind spot 28 is revealed by the testing structure of the invention. Thus, the invention provides a more sensitive testing structure. Slight plasma damage that cannot be detected by the old method can be detected with the new method. This model allows an accurate evaluation of plasma/charging damage of actual MOSFET's for the future VLSI era.