On-chip decoupling capacitors designed for a 0.11 micron and beyond dual gate oxide CMOS technology

#The present invention generally relates to an integrated circuit, and more particularly, to a decoupling capacitor for use in an integrated circuit.

#The extremely rapid switching rates of the discrete components that make up integrated circuits typically cause current transients in the power buses of the integrated circuits. These current transients may last for several nanoseconds. Unfortunately, for a given integrated circuit, the typical power supply driving the power bus requires an order of magnitude in the microsecond range to compensate for the current transients injected on the power bus by the discrete components. Moreover, the reduction in gate threshold voltage of the various discrete components in the integrated circuit requires the power bus to deliver a stable voltage signal having a minimum of voltage level variation. Consequently, power bus stability, in terms of current response and voltage level fluctuation, is a significant issue in the design of an integrated circuit.

#The conventional approach to provide power bus stability is the insertion of decoupling capacitors between the power bus and the one or more discrete components. However, the technical evolution of these discrete components has continued to realize a downwards scale to achieve density, speed and power improvements in the art of integrated circuit technology. With the development of new integrated circuit technologies and structures, the discrete devices forming the integrated circuit often have submicron structural dimensions. For example, in the field of metal oxide semiconductor field effect transistors (MOSFETs) the structure and design of MOSFET's continue to realize an ever shorter channel length between the source region and drain region of the MOSFET. The result of the trend toward ever shorter channel lengths yields a device that is easier to switch. Nevertheless, the gate oxide thickness of the device is merely a few layers of atoms and is approaching fundamental limits. For example, in a 0.11 micron complimentary metal-oxide-semiconductor (CMOS) device, the gate oxide electrical thickness is often less than two nanometers. Consequently, the reduced gate oxide thickness of a 0.04 micron CMOS short channel device makes the device prone to the effects of gate leakage current from other devices coupled thereto. One example is gate tunneling leakage current generated by one or more decoupling capacitors that couple the device to the power bus.

#An illustrative embodiment of the present invention will be described below relative to the following drawings.

#FIG. 1 depicts a block diagram of an exemplary integrated circuit suitable for practicing the illustrative embodiment of the present invention.

#FIG. 2 depicts schematic representation of a decoupling capacitor suitable for practicing the illustrative embodiment of the present invention.

#The illustrative embodiment of the present invention provides a decoupling capacitor having a thick gate oxide region to minimize and possibly avoid gate leakage current (for example, sub-threshold leakage current (IOFF) or other like leakage current components such as gate tunneling current, associated with the decoupling capacitor). In the illustrative embodiment, the decoupling capacitor is a long channel MOS device having a gate oxide region electrical thickness of between about 2.7 nanometers and about 3.3 nanometers. Those skilled in the art will recognize that the decoupling capacitor of the illustrative embodiment can also be structured as a short channel MOS device.

#In the illustrative embodiment, the decoupling capacitor is attractive for use in integrated circuits that utilize 0.11 micron or less, for example, 0.09 microns CMOS dual gate technology. The decoupling capacitor in the illustrative embodiment allows an integrated circuit, such as a microprocessor, to utilize 0.11 micron CMOS technology devices in circuits that require a high degree of stability, speed and reliability, (such as memory cells that have stringent leakage current requirements). The illustrative embodiment provides a significant reduction in leakage current in an integrated circuit and as such, allows an integrated circuit designer to avoid functional problems commonly associated with transistor leakage current. For example, the illustrative embodiment avoids a degradation of noise immunity in dynamic logic circuits, the compromise of stability in six transistor SRAM cells and the increase in leakage power consumption of the integrated circuit.

#FIG. 1 is a block diagram of an exemplary integrated circuit 10 that is suitable for practicing the illustrative embodiment of the present invention. The exemplary integrated circuit 10 includes a power bus 12 that distributes the power supply voltage VDD to the various circuits within the exemplary integrated circuit 10. Coupled to the power bus 12 is a decoupling capacitor 14, which, in turn, is coupled to a CMOS device 16. The decoupling capacitor 14, provides the CMOS device 16 with a stable voltage level VDD that is substantially free of voltage variation and also provides the CMOS device 16 with a minimum value of gate leakage current when the decoupling capacitor is in an on-state or an off-state. In the illustrative capacitor depicted in FIG. 1, the CMOS device 16 is a CMOS device with a channel length of about 0.04 micron. Because of the short channel effect of the CMOS device with a channel length of about 0.04 micron and its corresponding thin gate oxide layer, the 0.04 micron device is susceptible to leakage current associated with leaky decoupling capacitors coupled between the power bus 12 and the CMOS device 16. Those skilled in the art will appreciate that the decoupling capacitor 14 is able to provide significant improvements in various transistor leakage current components, such as transistor sub-threshold leakage current, gate induced drain leakage current, gate oxide tunneling current and other like transistor leakage current components.