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AssigneesRenesas Technology Corp., Mitsubishi Electric Engineering Company Limited
InventorTohru Kitano
Estimating the term…
A high impedance can be maintained at a back gate of a MOS transistor constituting a CMOS integrated circuit when power is not supplied, and is switched to an impedance lower than the impedance in use of the CMOS integrated circuit by a switch driven by a power supply of the CMOS integrated circuit. Thus, it is possible to prevent surge breakdown and electrostatic breakdown, and to prevent occurrence of latch up breakdown.
An electrostatic breakdown prevention circuit for a semiconductor device comprising:
An electrostatic breakdown prevention circuit for a semiconductor device comprising:
Dependencies are inferred from the claim text.
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For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using FETs as protective elements
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
Inorganic electric semiconductor devices
Term end not estimated
1) Field of the Invention
The present invention relates to a circuit which prevents electrostatic breakdown of MOS transistors constituting the semiconductor device (e.g. CMOS integrated circuit).
2) Description of the Related Art
FIGS. 1A to 1C are diagrams which show configurations of an electrostatic breakdown prevention circuit for a semiconductor device according to a first embodiment of the present invention,
FIG. 2 is a sectional structural view which explains the internal configuration of a CMOS inverter shown in FIG. 1C and the operation of the electrostatic breakdown prevention circuit,
FIG. 3 is a diagram which explains suppression of a thyristor operation by the electrostatic breakdown prevention circuit for the semiconductor device shown in FIG. 1,
Embodiments of the electrostatic breakdown prevention circuit for a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings.
A first embodiment of this invention will be explained below. FIGS. 1A to 1C are diagrams which show the configurations of the electrostatic breakdown prevention circuit for a semiconductor device according to the first embodiment. FIG. 1A shows an example of the configuration of an electrostatic breakdown prevention circuit for a PMOS transistor of the MOS transistors constituting a CMOS integrated circuit which is a semiconductor device. FIG. 1B shows an example of the configuration of an electrostatic breakdown prevention circuit for an NMOS transistor of the MOS transistors constituting the CMOS integrated circuit which is a semiconductor device. FIG. 1C shows an example of the configuration of an electrostatic breakdown prevention circuit for a CMOS inverter used in an output circuit.
In FIG. 1A, a PMOS transistor 1 has a source electrode S connected to a power supply (Vdd1) 2 and a drain electrode D connected to an electrode pad 3. A resistor 4, a PMOS transistor 5, and an inverter 6 are arranged for the PMOS transistor 1.