Damascene double-gate FET

#The present invention relates to double-gated field effect transistors (FETs), and in particular to a process of fabricating double-gated FETs wherein a damascene-like replacement gate processing step is employed to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench.

#In order to make integrated circuits (ICs) such as memory, logic and other devices, of higher integration density than currently feasible, one has to find a means to further scale down the FET devices that are present therein. Moreover, as FET dimensions are scaled down, it becomes increasingly difficult to control short-channel effects by conventional means. Short-channel effects, as well known to those skilled in the art, are the decrease in threshold voltage, V1, in short-channel devices, i.e., sub-0.1 micron, due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.

#An evolution beyond the standard single gate metal oxide semiconductor field effect transistor (MOSFET) is the double-gate MOSFET, where the device channel is confined between top and bottom gate dielectric layers. This structure, with a symmetrical gate structure, can be scaled to about half of the channel length as compared to a conventional single gate MOSFET structure. It is well known that a dual gate or double gate MOSFET device has several advantages over conventional single gate MOSFET devices. Specifically, the advantages for dual gate MOSFET devices over their single gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel dual gate MOSFET device and has shown that the dual gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET).

#FIGS. 1A-1B are pictorial representations of a plan view of the inventive FET structure and mask layout; 1A completed structure up to first-level metal, excluding gate contacts; 1B cut-away view showing where the silicon channel layer remains after etching and oxidization.

#FIGS. 2A-2D are cross-sectional representations of the inventive FET structure through various cuts shown in FIGS. 1A-1B.

#FIGS. 3-24 are cross-sectional representations of the inventive FET structure through various processing steps.

#The present invention, which provides a damascene-like gate replacement process of fabricating a double-gated field effect transistor (DGFET), will now be described in more detail by referring to the drawings that accompany the present application.

#Specifically, FIGS. 1 and 2 are top-down and sectional views, respectively of the DGFET of the present invention, while FIGS. 3-24 are representations of the structure through various processing steps of the present invention.

#Reference is first made to FIGS. 1A and 1B which is a plan view of the inventive FET structure and mask lay-out. FIG. 1A is the completed structure up to first-level metal, excluding gate contacts, whereas FIG. 1B is a cut-away view showing where the silicon channel layer remains in the structure after etching and oxidation. Note cut A-A′ is a cross-section though the top and bottom gate regions; cut B-B′ is a cross-section through an active area between the top and bottom gates, cut C-C′ is a cross-sectional view through an area adjacent to the top gate; and cut D-D′ is a cross-sectional view through the top gate only.