Nonvolatile memory cell for prevention from second bit effect

#The present invention relates generally to a semiconductor memory, and more specifically to a nonvolatile memory cell for prevention form second bit effect.

#Among semiconductor memories, the nonvolatile memory, especially the electrically erasable programmable read only memory (EEPROM), is particularly useful due to its advantage of retaining information even power is turned off, and its application also becomes more popular. Similar to other semiconductor memories, the nonvolatile memory is developed toward scale down to increase the memory capacity. New and improved memory cell structures and better programming mechanisms are proposed to improve the performance of nonvolatile memory. For example, a perpendicularly accelerated channel injection CMOS (PACMOS) is disclosed by M. Kamiya, Y. Kojima, Y. Kato, K. Tanada and Y. Hayashi, “EPROM cell with high gate injection efficiency”, IEDM Tech. Dig., 1982, pp 741-744, with a structure to enhance the channel injection to increase the injection efficiency. On the other hand, to increase the density of memory circuit and lengthen the electrical charge retention time, an oxide-nitride-oxide (ONO) structure has been used to replace conventional stack memory cell, which has the benefit of easy process and high density, for example, referring to T. Y. Chan, K. K. Young and Chenming Hu, “A true single-transistor oxide-nitride-oxide EEPROM device”, IEEE Electron Device Lett., vol. EDL-8, pp 93-95, 1987 and U.S. Pat. No. 5,168,334 issued to Mitchell et al. By storing two bits in a single memory cell the memory capacity can be doubled, for example, referring to U.S. Pat. Nos. 5,768,192, 5,963,465 and 6,011,725 issued to Eitan. However, new problems are introduced. Two bits stored in a single memory cell may cause interactions between each other of them, especially for the electric field from the stored charge of one bit to influence the other bit when the latter is manipulated. Or when one bit is manipulated, the voltage applied has effect on the other bit. One of the known undesired situation is called second bit effect, by which the threshold voltage of second bit is lowered due to the source side injection occurred in the transistor when writing the second bit and the electron packet of the first bit spreads to result in over writing. The adverse effect has a more serious impact on the shrunk devices. Therefore, it is desired a nonvolatile memory cell for prevention from second bit effect.

#One object of the present invention is to provide a nonvolatile memory cell to inhibit the second bit effect when writing data into the memory cell.

#These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is the cross-sectional view of a flash memory cell with an ONO programmable layer, in which the second bit effect is also shown;

#FIG. 2 is the top view of a MOS transistor with a gate of a funnel shape, in which the drain is wider than the source;

#FIG. 1 shows the cross-sectional view of an NMOS type flash memory cell 10, which is formed on a p+ substrate 12 with an heavily doped n+ source region 14 and drain region 16 with a channel region 18 therebetween and a programmable layer 20 above the channel region 18. In this embodiment, the programmable layer 20 has an ONO structure that includes an upper and lower oxides 22 and 24 with a nitride 26 inserted therebetween, by which the nitride 26 serves as a trapping dielectric layer where charge can be injected in and retained of at either one of its opposite sides. As is well known, other materials, such as oxide having buried poly-silicon islands, can also be used as the trapping dielectric layer. Above the programmable layer 20 is the gate conductor 28 formed of poly-silicon.

#FIG. 1 also illustrates the second bit effect. As shown, the memory cell 10 can store two bits, and under appropriate bias conditions the regions in the trapping dielectric layer 26 adjacent to the source/drain regions 14 and 16 can be written in one bit data, respectively, by hot electron injections 30 and 34 to form electron packets 32 and 36 within the nitride 26, thereby doubling the capacity of the memory cell 10. However, it is obviously that undesired situation may occur when manipulating two different bits in this structure for the reason that the bit under manipulation may be effectively influenced by the voltage applied to the transistor and the existence of the other bit. In particular, during writing data into a second bit the source side injection is likely to occur in the cell transistor 10, as indicated by arrow 30 in FIG. 1, resulting in threshold voltage lowering of the second bit and electron packet spreading of the first bit and over writing consequently.

#The aforementioned second bit effect is resulted from the source side injection, and thus modifying the cell transistor structure may influence the performance of the transistor. The characteristic of substrate current is widely used as a tool to observe hot carrier effect. To understand the principle of the present invention, a known concept is introduced herewith. FIGS. 2 and 3 illustrate two MOS devices with gates of a funnel shape. In the transistor of FIG. 2, its drain region 38 is wider than the source region 40 and the gate 42 is of a funnel shape that is getting gradually narrower from the drain region 38 to the source region 40, by which the device is observed to have a phenomenon of source injection. Contrarily, in the transistor of FIG. 3 the source region 44 is wider than the drain region 46 and its gate 48 is also of a funnel shape, however, that is getting gradually narrower from the source region 44 to the drain region 46, in which the device does not have the source injection. For details on the double peak substrate current of such transistors with gate of a funnel shape, reader is referred to T. Y. Huang and J. Y. Chen, “Observation of double-hump substrate current in funnel-shape transistors”, IEEE Electron Device Lett., vol. EDL-6, pp 510-512, 1985.