Test patterns and methods of controlling CMP process using the same

#This application claims priority to Korean Patent Application No. 2002-19670, filed on Apr. 11, 2002.

#The present invention relates generally to semiconductor devices and, more particularly, to test patterns and methods of controlling chemical mechanical polishing (CMP) using the same.

#As integration of semiconductor devices increases and multi-layer interconnection processes are more readily applied, global planarization of interlayer dielectric layers is becoming increasingly important. While variable techniques have been used for the global planarization, CMP processes have been widely used in recent years due to numerous well-known advantages.

#FIGS. 1 through 4 are cross-sectional views illustrating a conventional CMP process;

#FIG. 5 is a schematic top plan view of a typical semiconductor substrate;

#FIGS. 6 and 7 are top plan views of a test pattern according to a preferred embodiment of the present invention;

#The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout.

#FIG. 5 is a schematic top plan view of a typical semiconductor substrate.

#Referring to FIG. 5, a semiconductor substrate 50 includes main regions b arranged in a matrix, in each of which semiconductor devices will be formed. After processes of fabricating devices are complete, the main regions are disposed at regular intervals to be separated from each other. In fabrication processes of semiconductor devices, test patterns are required for monitoring each process. The test patterns are formed to various shapes according to each process and are disposed at regions between the main regions b. That is, the regions between the main regions b correspond to monitoring regions a where the test patterns are disposed.