US 2003/0191550 A1 · Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's undergo, such as additional repairs

Abstract

An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

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Drawings

Claims20

Dependent claims

A manufacturing process for a memory device having a substantially unique identification code using data for manufacturing processes for a plurality of memory devices to select manufacturing processes for each of the memory devices, the process comprising:

storing data using a substantially unique identification code of each of said memory devices for identifying manufacturing processes for the memory devices, the storing data including storing data for identifying repairs performed on each of said memory devices and for identifying spare rows and columns available to effect repairs in each of said memory devices;
automatically reading the substantially unique identification code of each said memory devices;
accessing the data stored in association with the substantially unique identification code of each of said memory devices;
selecting manufacturing processes for each of said memory devices using the accessed data;
and
assembling acceptable memory devices of said memory devices into packaged memory devices.

3 more elements

A manufacturing process for integrated circuit devices from semiconductor wafers comprising:

fabricating a plurality of devices on each semiconductor wafer of the plurality of semiconductor wafers;
storing in each device of the devices on each semiconductor wafer of the plurality of semiconductor wafers a substantially unique identification code;
storing data using the substantially unique identification code of each device of the devices for identifying manufacturing procedures for the devices;
separating each of the devices on each semiconductor wafer of the plurality of semiconductor wafers for forming one die of a plurality of dice;
assembling each die of the plurality of dice into a semiconductor device, the assembling including:
picking each die of the plurality of dice from its semiconductor wafer;
placing each die of the plurality of dice onto an epoxy-coated bonding site of one lead frame of a plurality of lead frames;
curing the epoxy on the bonding site of each lead frame of the plurality of lead frames;
connecting each die of the plurality of dice to an associated member;
encapsulating each die of the plurality of dice and its associated member for forming one package of a plurality of packages;
automatically reading the substantially unique identification code associated with each semiconductor device package of the plurality of semiconductor devices packages;
and
accessing the data stored using the substantially unique identification code associated with each semiconductor device package of the plurality of semiconductor device packages.

10 more elements

Dependencies are inferred from the claim text.

Description5,720 words

Summary2,239 words

#1. Field of the Invention

#The present invention relates in general to integrated circuit (IC) manufacturing. More specifically, it relates to methods in IC manufacturing processes for using data regarding manufacturing procedures IC's have undergone, such as repair procedures, to select procedures the IC's will undergo, such as additional repair procedures.

#2. State of the Art

Brief description of the drawings6 figures

#FIG. 1 is a flow diagram illustrating a conventional integrated circuit (IC) device manufacturing process;

#FIG. 2 is a flow diagram illustrating a conventional Chip-On-Board (COB) or flip-chip attached IC manufacturing process;

#FIG. 3A is a flow diagram illustrating an IC device manufacturing process in accordance with the present invention;

Detailed description3,368 words

#As shown in FIG. 3A, an inventive process 30 for manufacturing Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) devices begins with DRAM IC's being fabricated in a fabrication step 32 on the surface of a semiconductor wafer 34. It will be understood by those having skill in the field of this invention that the present invention is applicable to any IC devices, including Static Random Access Memory (SRAM) IC's, Synchronous DRAM (SDRAM) IC's, processor IC's, Single In-line Memory Modules (SIMM's), Dual In-line Memory Modules (DIMM's), and other Multi-Chip Modules (MCM's). It will also be understood that although the present invention will be described below in the context of a wire bond/lead frame assembly process, the present invention is applicable to any IC assembly process, including, for example, Chip On Board (COB) and flip-chip processes (as will be described below with respect to FIGS. 4A and 4B), and Tape-Automated Bonding (TAB) processes.

#Once fabricated, the DRAM IC's are electronically probed in a probe step 36 to determine whether they are good or bad, and if any DRAM IC's are found to be bad, an attempt is made to repair those IC's by replacing nonfunctional rows or columns in the IC's with spare rows or columns. The location of bad DRAM IC's on a wafer 34, along with the location of any good DRAM IC's on the wafer 34, is stored in a computer in an electronic wafer map in association with data identifying spare rows and columns still available in each of the DRAM IC's after any repairs performed at the probe step 36. Of course, it will be understood that the stored data may alternatively identify spare rows and columns used in each of the DRAM IC's to effect repairs at the probe step 36.

#During the probe step 36, DRAM IC's fabricated on the wafers 34 are programmed in the manner described above with a fuse identification (ID) unique to each IC. The fuse ID for each DRAM IC is then stored in association with the repair data 38 for that IC. The fuse ID may identify, for example, a wafer lot ID, the week the DRAM IC's were fabricated, a wafer ID, a die location on the wafer, and a fabrication facility ID. As a result of storing the fuse ID for each DRAM IC in association with the repair data 38, the availability of spare rows or columns for effecting post-probe repairs in a particular DRAM IC can be determined by using the fuse ID of the IC to access the stored repair data 38 for the IC, as will be described in more detail below.

Facts

Application

10/401,209Filed 27 Mar 2003

Priority

6 Jun 1997

Published

9 Oct 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 11/006
Error detection; Error correction; Monitoring: identification
H10W 46/403
For identification or tracking: for non-wireless electrical read out
G06F
Computing and data processing
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

Application08/871,015Continuation · filed 6 Jun 1997

Application09/292,655Continuation · filed 15 Apr 1999

Application10/071,961Continuation · filed 5 Feb 2002

Application10/401,209Continuation · filed 27 Mar 2003

US 2002/0082740 A1Published application

US 5,907,492 ARelated patent

US 6,363,295 B1Related patent

US 6,553,276 B2Related patent

US 7,155,300 B2Related patent

US 2003/0191550 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

6 Jun 1997Priority claimedParent application 08/871,015
27 Mar 2003Application filedUS 10/401,209
9 Oct 2003Published
12 May 2016Assigned to U.S. Bank National Association, AS Collateral Agentsecurity interest
2 Jun 2016Assigned to Morgan Stanley Senior Funding, Inc., AS Collateral Agentpatent security agreement
8 Jun 2017Assigned to U.S. Bank National Association, AS Collateral Agentcorrective assignment to correct the replace erroneously filed patent #7358718 with the correct patent #7358178 previously recorded on reel 038669 frame 0001. assignor(s) hereby confirms the security interest.
23 Aug 2018Assigned to Micron Technology, Inc.release of security interest
9 Oct 2019Assigned to Micron Technology, Inc.release of security interest

Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's undergo, such as additional repairs

Life of this patent

Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's undergo, such as additional repairs

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description5,720 words

Drawings

Classification4 codes

Life of this patent

Description5,720 words