Dual damascene barrier structures and preferential etching method

#The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structures and processes in integrated circuit fabrication aiming at interconnected multi-level copper metallization.

#In the last few years, copper interconnection has been adapted to silicon integrated circuits due to its low resistance and high electromigration reliability compared to the traditional aluminum interconnection. Single-damascene and dual-damascene methods have been employed for the fabrication of copper interconnection. For multi-level copper interconnects using any of these two methods, improved electromigration reliability, especially improved lifetime of early failures have been reported, for example, in the recent article “A High Reliability Copper Dual-Damascene Interconnection with Direct-Contact Via Structure” (K. Ueno et al, IEEE Internat. Electron Devices Meeting Dec. 10-13, 2000, pp. 265-268). In the technique described, the improvement in multi-level copper circuits has been achieved by making the copper contacts on the bottom of interconnecting vias barrier-free except for an ultra-thin adhesion layer.

#In spite of progress such as described in that paper, in known technology many problems still remain related to the copper interconnection concept. For example, the copper traces have to be sealed by barrier layers in order to prevent copper migration into the silicon circuitry where copper atoms are known to offer energy levels for electron recombination/generation, acting as electron life-time killers. The same sealing barriers should protect the porous insulating layers of low dielectric constant (so-called low-k materials) against intruding atoms, which may initiate coalescence of micro-voids into larger voids.

#FIG. 1 shows a schematic cross section through a stack of insulating layers, alternating between etch stop and dielectric layers, over the (n−1) level metal line.

#FIG. 2 shows the schematic cross section after the via has been etched through the top etch stop and the top dielectric layer.

#FIG. 3 shows the schematic cross section after the trench has been etched, while the via has been etched to the bottom stop layer.

#The present invention is related to U.S. patent applications Ser. No. 09/863,687, filed on May 23, 2001 (Brennan et al., “Method for Sealing Via Sidewalls in Porous Low-k Dielectric Layers”); Ser. No. 09/917,364, filed on Jul. 27, 2001 (Brennan et al., “Method of Fabricating Interlevel Connectors using only one Photomask Step”); Ser. No. 09/975,571, filed on Oct. 11, 2001 (Jiang, “Reducing Copper Line Resistivity by Smoothing Trench and Via Sidewalls”); and TI Ser. No. 32156, filed on Mar. 27, 2002 (Jiang et al., “Copper Transition Layer for Improving Copper Interconnection Reliability”).

#Single-damascene and dual-damascene processes have been used to fabricate copper interconnections. This invention applies to both of these technologies. The dual-damascene technology has the advantage of reducing process steps which leads to lower cost. It is, therefore, chosen as the vehicle to describe the present invention. It should be stressed, however, that this invention applies also to the single-damascene technology.

#FIG. 1 is a schematic representation of a dual-damascene interlevel structure, generally designated 100; FIG. 1 is generic and not to scale. A first level horizontal metal interconnector line has been produced, located on, or imbedded in, an insulated semiconductor substrate 102. This level of metallization is marked as (n−1) level in order to indicate that a multi-level hierarchy of metal levels is considered. In this invention, line 101 is made of copper.