Method of loading a wafer onto a wafer holder to reduce thermal shock

#This application hereby incorporates by reference the entire disclosures of: (1) U.S. Pat. No. 4,821,674 to de Boer, et al.; (2) U.S. Pat. No. 6,293,749 to Raaijmakers et al.; and (3) U.S. patent application Ser. No. 09/747,173, entitled “Susceptor Pocket Profile to Improve Process Performance,” filed Dec. 22, 2000.

#This invention relates generally to the processing of wafers within semiconductor processing chambers and, more particularly, to a method of loading a wafer onto a wafer holder within a cold wall chemical vapor deposition chamber.

#High-temperature ovens, or reactors, are used to process semiconductor wafers from which integrated circuits are made for the electronics industry. A substrate, typically a circular silicon wafer, is placed on a wafer holder. If the wafer holder helps to attract heat, it is called a susceptor. The wafer and wafer holder are enclosed in a quartz chamber and heated to high temperatures, such as 600-1200° C. or even higher, by a plurality of radiant lamps placed around the quartz chamber. A reactant gas is passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer of the reactant material on the wafer. Through subsequent processes in other equipment, these layers are made into integrated circuits, with a single layer producing from tens to thousands of integrated circuits, depending on the size of the wafer and the complexity of the circuits. In recent years, single-wafer processing has grown for a variety of reasons, including its greater precision as opposed to processing batches of wafers at the same time, while larger diameter wafers are employed to compensate for reduced throughput as compared to batch processing.

#FIG. 1 is a schematic, cross-sectional view of an exemplary reaction chamber within which a wafer can be loaded onto a wafer holder in accordance with the methods of the present invention; and

#FIGS. 2-7 are schematic, cross-sectional views of a portion of the reaction chamber of FIG. 1, illustrating a method of loading a wafer onto a wafer holder in accordance with a preferred embodiment of the present invention.

#As explained above, prior art methods for preheating a wafer as it is loaded into a reaction chamber are often too slow to result in optimal throughput. On the other hand, direct loading of a cold wafer onto a hot wafer holder, while less time-consuming, can result in thermal shock. The present invention provides a middle ground between these avenues, resulting in optimal throughput while substantially preventing thermal shock.

#The present invention includes methods of preheating and loading a semiconductor wafer onto a wafer holder inside a reaction chamber. FIG. 1 illustrates one type of reaction chamber within which a wafer can be loaded according to the invention. However, the skilled artisan will understand from the teachings herein that the methods of the invention can be employed for many different types of wafer holders and reaction chambers. The discussion herein should not be limited to one particular type of reaction chamber or wafer holder. Moreover, while illustrated in the context of standard silicon wafers, the invention described herein can be used to load other kinds of substrates, such as glass, which are subjected to high temperature treatments such as CVD, physical vapor deposition (PVD), etching, annealing, dopant diffusion, photolithography, etc. The methods of the invention are of particular utility for loading substrates for processing at elevated temperatures, and even more particularly for processes in which relatively cold wafers (e.g., room temperature) are loaded onto hot relatively (e.g. 600° C. or higher) wafer holders. As used herein, the terms “substrate” and “wafer” have the same meaning.

#FIG. 1 illustrates one type of cold wall reaction chamber 20 into which a semiconductor wafer can be loaded according to the methods of the present invention. Prior to discussing the details of the invention, the elements of the reaction chamber 20 will be described. The chamber 20 includes a wafer holder in the form of a susceptor system 22. While FIG. 1 illustrates a susceptor, other types of wafer holders can alternatively be used. The chamber 20 comprises a quartz tube defined by an upper wall 24, a lower wall 26, an upstream flange 28, and a downstream flange 30. Although not shown in the figure, lateral edges of the reaction chamber 20 include relatively thick side rails between which a chamber divider plate 32 is attached. FIG. 1 is a longitudinal cross-section along a central vertical plane of the chamber 20 illustrating its vertical dimension; the side rails are thus not seen. Preferably, the chamber 20 is manufactured from quartz. The chamber divider plate 32 reinforces the chamber 20 during vacuum processing and extends between the side rails (not shown), preferably along the centerline of the chamber 20. The divider plate 32 includes an aperture 33 defining a void or opening 35 extending across the lateral dimension of the chamber 20 between the side rails. The aperture 33 divides the divider plate 32 into an upstream section extending from the upstream flange 28 to an upstream edge of the aperture 33, and a downstream section extending from a downstream edge of the aperture to the downstream flange 30. The upstream section of the divider plate 32 is preferably shorter in the longitudinal direction than the downstream section.