Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices
AssigneeInfineon Technologies AG
InventorsPeter Lahnor, Alexander Simpson
Life of this patent
Estimating the term…
Abstract
A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.
Claims21
A process for treating a process layer applied to a working surface of a semiconductor device, the process layer having a structure formed of recessed sections and elevated sections, which comprises the steps of:
- applying an auxiliary substance to the process layer resulting in the recessed sections being at least partially filled with the auxiliary substance and a filled process layer being formed;
- and
- reducing in height the filled process layer down to the working surface, using a polishing device, resulting in the working surface being planarized.
A process for treating a process layer applied to a working surface of a semiconductor device, the process layer having a structure formed of recessed sections and elevated sections, which comprises the steps of:
- applying an auxiliary substance to the process layer resulting in the recessed sections being at least partially filled with the auxiliary substance and a filled process layer being formed, a resistance of the auxiliary substance being adjusted in dependence on a topology of the process layer;
- and
- reducing in height the filled process layer down to the working surface using a polishing device resulting in the working surface being simultaneously planarized via the polishing device and a same procedure for different topologies of the structure.
Dependencies are inferred from the claim text.