Method for forming a metal extrusion free via

#The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for forming vias in semiconductor devices.

#A continuing trend in semiconductor manufacturing is to make more powerful and complex integrated circuit devices in a smaller area. Manufacturers achieve this objective by making individual feature sizes smaller and by locating these features closer together. Millions of active and passive devices, such as transistors, capacitors, and resistors are formed on a semiconductor substrate, such as silicon. These devices are isolated from each other on the substrate and later are interconnected to form functional circuits. The quality of these interconnecting structures drastically affects the performance, and reliability of the completed circuits.

#Often the interconnections are fabricated as a multilayer structure having alternating layers of patterned metal and dielectric materials. The dielectric layers, frequently a form of silicon oxide, serve to separate the conductors, both vertically and horizontally, and very small, vertical metal filled vias provide a means of interconnection between the metal levels. Performance of the interconnections and dielectric must be precise and predictable in order to provide a stable device.

#FIG. 1 is a cross sectional view of a via structure. (prior art)

#FIG. 2 is a cross section of a via having a metal extrusion through the barrier layers. (Prior art)

#FIG. 3 is a cross section of via of a preferred embodiment of the current invention.

#The cross section of a via known to prior art, as illustrated in FIG. 1, is similar to that of the current invention. However, in practice, it should be recognized that the layers are not perfectly smooth, that the thickness of each layer may not be uniform, and that the features may not be as well aligned, as shown. Further, a more detailed look at a cross section of a via of a preferred embodiment of the current invention, as shown in FIG. 3 includes a reacted layer of titanium aluminide 304 in the metal stack. The titanium aluminide, primarily existing as TiAl3, has advantages of serving as a via etch stop, an electromigration resistance improvement, and as a barrier against aluminum extrusions or hillocks. These advantages of the titanium aluminide layer are not novel, and are not a subject of the invention; but integrity of the layer, that of the total via, and of the via barrier against metal extrusions is critical, and is the subject of the invention. Lacking integrity of the reacted metal layer and the via barrier, the metallurgical junctions may be unstable due to the presence of metal extrusions and the aluminide interface. The disturbed interface can react and form voids under the via due to a volume reduction associated with the titanium aluminide reaction. Further, aluminum in the interconnection line can diffuse away from the junction and result in mechanically induced stress migration.

#In the preferred embodiment, the metal stack includes the interconnection line 301 of aluminum (Al) doped with copper (Cu), and sandwiched between reactive titanium (Ti) sticking layers. A titanium nitride (TiN) 306 or silicon oxynitride layer on the first surface 311 of the metal stack serves as an anti-reflective coating (ARC).

#A sticking layer of titanium 308 lies directly under the CVD deposited titanium nitride via barrier layer 307 which covers both the side walls and bottom of the etched via hole. The via has been patterned and etched into a dielectric material 302, comprised of one or more layers of an oxide. The via hole in filled with a tungsten plug 303.