Pattern formation process for an integrated circuit substrate
AssigneeVIA Technologies, Inc.
InventorsMoriss Kung, Kwun-Yao Ho
Life of this patent
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Abstract
A pattern formation process for an integrated circuit substrate, which is not employing the conventional method of filling resin material directly in via filling process but adapting the metal spray method, the metal vapor deposition method or any combination thereof to form the pattern including circuits and pads and stuff the vias and the through holes.
Claims17
A conductive through hole formation process on an integrated circuit substrate, which comprising at lease the following steps:
- (a) providing a substrate, and placing a release film on the substrate;
- (b) forming at lease one through hole penetrating through the substrate and the release film;
- (c) filling up the through hole by applying one of the methods of the metal spray, the metal vapor deposition, and the combination of both to form the conductive through hole in the substrate;
- and
- (d) removing the release film.
A pattern formation process for an integrated circuit substrate, which comprising at least the following steps:
- (a) providing a substrate, which already be finished the previous processes, with a dielectric layer on at least one surface;
- (b) defining at least one via opening and a pattern simultaneously on the dielectric layer;
- (c) forming a metal layer by applying one of the methods of the metal spray, the metal vapor deposition, and the combination of both on the substrate to fill up the via opening and form the conductive pattern;
- and
- (d) proceed a planarization process on the metal layer.
A pattern formation process for an integrated circuit substrate, which comprising at least the following steps:
- (a) providing a substrate, which already be finished the previous processes, with a dielectric layer on at least one surface;
- (b) defining at least one via opening on the dielectric layer;
- (c) forming a metal layer by applying one of the methods of the metal spray, the metal vapor deposition, and the combination of both on the substrate to fill up the via opening;
- and
- (d) proceed a planarization process on the metal layer.
Dependencies are inferred from the claim text.