Method for manufacturing a semiconductor device having a layered gate electrode

#(a) Field of the Invention

#The present invention relates to a method for manufacturing a semiconductor device having a layered gate electrode and, more particularly, to a method for forming an improved structure of the layered gate electrode including a polysilicon film and a metal silicide film.

#(b) Description of the Related Art

#FIGS. 1A to 1E are sectional views of a semiconductor device during consecutive steps of a fabrication process thereof according to an embodiment of the present invention.

#FIG. 2 is a graph showing product yields of the non-defective MOSFETs and the refresh time of a resultant DRAM, which are plotted against the amount of side oxidation for the gate electrode.

#FIGS. 3A to 3D are sectional views of a semiconductor device during consecutive steps of a conventional fabrication process thereof.

#Now, the present invention is more specifically described with reference to accompanying drawings, wherein similar constituent elements are designated by similar reference numerals.

#Referring to FIGS. 1A to 1E, there is shown a fabrication process of a DRAM, i.e., a semiconductor device according to an embodiment of the present invention. An element isolation structure and diffused regions are formed on a semiconductor (silicon) substrate 11, followed by consecutive deposition of a 7 nm-thick gate oxide film 12, a 100-nm-thick polysilicon film 13, a 120-nm-thick tungsten silicide film 14, and a 200-nm-thick silicon nitride film (not shown). Subsequently, a photoresist pattern 15 is formed thereon using a photolithographic technique, followed by patterning the silicon nitride film by an anisotropic etching technique using the photoresist pattern 15 as an etching mask, thereby forming a nitride hard mask 16 to obtain the structure shown in FIG. 1A.

#Thereafter, the photoresist mask 15 is removed, followed by etching the tungsten silicide film 14 by using the nitride hard mask 16 as an etching mask and depositing thereon a 10-nm-thick polysilicon film 17, as shown in FIG. 1B. The polysilicon film 17 effectively protects the side surfaces of the tungsten silicide film 14 during the subsequent step. The polysilicon film 17 thus deposited and the underlying polysilicon film 13 are then subjected to an anisotropic selective etching process to form a gate electrode pattern. After this etching process, the etched polysilicon film 13 has a width somewhat larger than the width of the tungsten silicide film 14 so that part of the polysilicon film 17 covering the side surfaces of the tungsten silicide film 14 is left as a 5-nm-thick side-wall polysilicon film 18, as shown in FIG. 1C.