Memory manufacturing process with bitline isolation

A method of manufacturing an integrated circuit comprising:

• providing a silicon substrate having a core region and a periphery region;
• depositing a charge-trapping dielectric layer over the silicon substrate in the core region;
• depositing a gate dielectric layer over the silicon substrate in the periphery region;
• implanting bitlines in the silicon substrate;
• depositing a wordline-gate layer over the charge-trapping dielectric layer and the gate dielectric layer;
• processing a periphery photoresist layer over the wordline-gate layer to cover the periphery region;
• implanting the wordline-gate layer with dopant in the core region to form a wordline implant;
• removing the periphery photoresist layer;
• forming a wordline having the wordline implant and a gate;
• forming spacers around the wordline and the gate;
• processing a core photoresist layer over the wordline and the gate to cover the core region;
• implanting the silicon substrate around the spacer around the gate with source/drain junctions and the gate with a gate doping implantation;
• and
• removing the core photoresist layer.

A method of manufacturing an integrated circuit comprising:

• providing a p-type silicon substrate having a core region and a periphery region;
• depositing a charge-trapping dielectric layer over the p-type silicon substrate in the core region;
• depositing a gate oxide over the p-type silicon substrate in the periphery region;
• implanting n-type bitlines in the p-type silicon substrate;
• depositing a polysilicon layer over the charge-trapping dielectric layer and the gate oxide;
• processing a periphery photoresist layer over the polysilicon layer to cover the periphery region;
• implanting the polysilicon layer in the core region to have a wordline implant;
• removing the periphery photoresist layer;
• forming a polysilicon wordline with the wordline implant and a polysilicon gate;
• forming a spacer around the polysilicon wordline and the polysilicon gate;
• processing a core photoresist layer over the polysilicon wordline and the polysilicon gate to cover the core region;
• implanting the p-type silicon substrate around the spacer with source/drain junctions and the polysilicon gate with a gate doping implantation;
• and
• removing the core photoresist layer.