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AssigneeMacronix International Co., Ltd.
InventorsChien-Hung Liu, Shyi-Shuh Pan, Shou-Wei Huang
Estimating the term…
A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.
A method of fabricating a nitride read only memory, comprising:
A method of fabricating a nitride read only memory, comprising:
A method of fabricating a semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Backward citations are indexed for grants only.
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Semiconductor device manufacturing: process: forming tapered edges on substrate or adjacent layers
Electronic memory devices
Term end not estimated
This application claims the priority benefit of Taiwan application serial no. 91106949, filed on Apr. 8, 2002.
1. Field of the Invention
The invention relates in general to a method of fabricating a memory, and more particularly, to a method of fabricating a nitride read only memory (NROM).
FIG. 1A to FIG. 1C are cross sectional views showing the conventional method of fabricating a nitride read only memory; and
FIG. 2A to FIG. 2E are cross sectional views showing the method of fabricating a nitride read only memory according to the invention.
FIG. 2A to FIG. 2E are cross sectional views showing the method of fabricating a nitride read only memory according to the invention.
In FIG. 2A, a substrate 200 is provided. An insulation layer 202 is formed on the substrate 200. The material of the insulation layer 202 includes silicon oxide, for example, and the method for forming the insulation layer 202 includes a thermal process of which the substrate 200 is disposed in a furnace. A charge trap layer 204 is formed on the insulation layer 202. The material of the charge trap layer 204 includes silicon nitride layer formed by chemical vapor deposition with silane and ammonia as the gas sources, for example. An insulation layer 206 is formed on the charge trap layer 204. The material of the insulation layer 206 includes silicon oxide formed by low pressure chemical vapor deposition with silane and nitrogen monoxide as gas sources, or using thermal oxidation to oxidize the charge trap layer 204, for example. The insulation layer 202, the charge trap layer 204 and the insulation layer 206 construct a dielectric trapping sandwiched structure.
In FIG. 2B, a pattern transfer layer 208, for example, a photoresist layer, is formed on the insulation layer 206. Using the pattern transfer layer 208 as a mask, the substrate 200 is implanted with ions to form a source/drain region. Portions of the insulation layer 206 and the charge trap layer 204 are removed with the pattern transfer layer 208 as a mask to form an opening 210. The method for forming the opening 210 includes anisotropic etching that has the following conditions. While starting to etch the insulation layer 206, an operation pressure is ranged between about 10 mtorr to about 100 mtorr, and the operation power is ranged from about 100W to about 500W. When etching reaches a bottom of the insulation layer 206, the operation power is ranged between about 1 W and about 100W, and the flow rate of the etching gas, carbon tetrafluoride, is adjusted to about 50 sccm to about 200 sccm. While starting etching the charge trap layer 204, the operation pressure is between about 10 mtorr to about 100 mtorr, and the operation power is from about 200W to about 800W. While reaching the bottom of the charge trap layer 204, the operation power is about 1W to about 100W, and the etching gas includes hydrogen bromide with a flow rate from about 10 sccm to about 50 sccm, and sulfur hexafluoride with a flow rate of about 10 sccm to about 50 sccm.