Method of forming a semiconductor array of floating gate memory cells and strap regions
AssigneeSilicon Storage Technology, Inc.
InventorsChih Hsin Wang, Amitay Levi
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AssigneeSilicon Storage Technology, Inc.
InventorsChih Hsin Wang, Amitay Levi
Estimating the term…
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.
An array of electrically programmable and erasable memory devices comprising:
An array of electrically programmable and erasable memory devices comprising:
A method of forming an array of memory devices, the method comprising the steps of:
A method of forming an array of memory devices, the method comprising the steps of:
Dependencies are inferred from the claim text.