US 2003/0176042 A1 · Methods for fabricating a compound semiconductor protection device for low voltage and high speed data lines

Abstract

The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients. A protection circuit can be monolithically integrated with the protected circuit or can be packaged in a separate integrated circuit.

Claims32

Dependent claims

A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:

providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate;
an N+ sub-collector layer;
an N-type collector layer;
a P-type base layer;
and
an N-type emitter layer;
removing selected portions of the N-type emitter layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type emitter layer is used to fabricate emitters for transistors;
removing selected portions of the P-type base layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type base layer is used to fabricate bases for transistors and anodes for steering diodes;
removing selected portions of the N-type collector layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes;
isolating regions in the N+ sub-collector layer such that transistors and steering diodes are electrically isolated;
forming an insulating layer on selected portions the substrate assembly;
and
forming electrical connections to the transistors and steering diodes.

11 more elements

A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:

providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate;
an N+ sub-collector layer;
an N-type collector layer;
a P-type base layer;
and
an N-type emitter layer;
removing selected portions of the N-type emitter layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type emitter layer is used to fabricate emitters for transistors and cathodes for breakdown diodes;
removing selected portions of the P-type base layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the P-type base layer is used to fabricate bases for transistors, anodes for steering diodes, and anodes for breakdown diodes;
removing selected portions of the N-type collector layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes;
isolating regions into the N+ sub-collector layer such that transistors, steering diodes, and breakdown diodes are electrically isolated;
forming an insulating layer on selected portions the substrate assembly;
and
forming electrical connections to the transistors, steering diodes, and breakdown diodes.

11 more elements

A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:

providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate;
a P+ sub-collector layer;
a P-type collector layer;
an N-type base layer;
and
a P-type emitter layer;
removing selected portions of the P-type emitter layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type emitter layer is used to fabricate emitters for transistors;
removing selected portions of the N-type base layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type base layer is used to fabricate bases for transistors and anodes for steering diodes;
removing selected portions of the P-type collector layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes;
isolating regions into the P+ sub-collector layer to isolate transistors and steering diodes;
forming an insulating layer on selected portions the substrate assembly;
and
forming electrical connections to the transistors and steering diodes.

11 more elements

A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:

providing a monolithic, epitaxially-grown substrate, wherein the substrate assembly includes:
a semi-insulating substrate;
an N+ sub-collector layer;
an N-type collector layer;
a P-type base layer;
and
an N-type emitter layer;
forming a transistor by:
removing a first portion of the N-type emitter layer, a first portion of the P-type base layer, and a first portion of the N-type collector layer from around a second portion of the N-type emitter layer, a second portion of the P-type base layer, and a second portion of the N-type collector layer;
and
isolating a first portion of the N+ sub-collector layer by ion implantation, where the ion-implanted first portion of the N+ sub-collector layer isolates a second portion of the N+ sub-collector layer from at least a third portion of the N+ sub-collector layer;
forming a steering diode by:
removing a third portion of the N-type emitter layer, where the removed third portion of the N-type emitter layer removes substantially all of a portion of the N-type emitter layer above a third portion and a fourth portion of the P-type base layer;
removing the third portion of the P-type base layer and a third portion of the N-type collector layer from around the fourth portion of the P-type base layer and a fourth portion of the N-type collector layer;
and
using the fourth portion of the P-type base layer and the fourth portion of the N-type collector layer as an anode and a cathode, respectively, of the steering diode;
and, coupling at least two steering diodes on the substrate assembly to protect a transistor on the substrate assembly from an undesired voltage transient.

14 more elements

Dependencies are inferred from the claim text.

Methods for fabricating a compound semiconductor protection device for low voltage and high speed data lines

Life of this patent

Methods for fabricating a compound semiconductor protection device for low voltage and high speed data lines

Life of this patent

Abstract

Claims32