Method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes

Abstract

A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least %, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.

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