Multi-layer structure for reducing capacitance and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYu-Sik Kim, Joong-Hee Lee
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Abstract
The invention relates to a multi-layer structure used in an optical communication field and its manufacturing method in which the capacitance effect between the metal patterns of a Silicon Optical Bench (SiOB) is significantly reduced. The multi-layer structure includes a dielectric layer and conductive patterns on a semiconductor substrate, such that the conductive patterns are separated from each other, wherein the dielectric layer and upper portions of the semiconductor substrate between the conductive patterns are etched out to a predetermined thickness to effectively reduce the capacitance without changing the area or structure of the metal patterns.
Claims14
A multi-layer structure for reducing capacitance thereon, comprising:
- a dielectric layer deposited on a semiconductor substrate;
- and,
- at least two conductive patterns, separated by a predetermined distance, formed on the semiconductor substrate,
- wherein the dielectric layer and upper portions of the semiconductor substrate between the conductive patterns are etched out to a predetermined thickness.
A method of manufacturing a multi-layer structure, the method comprising the steps of:
- (a) forming a dielectric layer on a silicon substrate;
- (b) forming at least two metal patterns separate from each other on the dielectric layer;
- and,
- (c) etching the dielectric layer and an upper layer of the silicon substrate between the metal patterns to a predetermined thickness.
The method of Clam 7 wherein the step (c) comprises the step of:
- dry-etching the dielectric layer and subsequently over-etching to remove the upper layer of the silicon substrate while using the metal patterns as an etching mask.
The method of Clam 7 wherein the etched-out portions of the silicon substrate between the metal patterns have a thickness of 0.5-2 μm.
Dependencies are inferred from the claim text.