Electrostatic discharge protection in double diffused MOS transistors

A method for fabricating an DMOS transistor integrated with an electrostatic protection structure (ESD) in a common substrate, the substrate comprising a silicon body covered with an epitaxial silicon layer, the epitaxial layer having a first region for the DMOS transistor and designated the DMOS region, a second region for the ESD designated the ESD region, and an isolation space between the DMOS region and the ESD region, the method comprising the steps of:

• a. growing an MOS gate dielectric layer on the DMOS region,
• b. depositing a polysilicon gate layer on the MOS gate dielectric layer,
• c. selectively etching the polysilicon gate layer to form a polysilicon gate on a portion of the gate dielectric layer,
• d. selectively implanting p-type impurities simultaneously into:
• i. a first DMOS region adjacent to the polysilicon gate, and
• ii. a first ESD region,
• e. selectively implanting n-type impurities simultaneously into:
• i. a second DMOS region adjacent to the polysilicon gate to form a source,
• ii. a third DMOS region spaced from the polysilicon gate to form a drain, and
• iii. the first ESD region to form a p-n junction diode,
• f. implanting n-type impurities into the silicon substrate to form a lightly doped drain (LDD) between the polysilicon gate and the drain,
• g. etching the epitaxial layer in the isolation space to produce a trench extending from the surface of the substrate to the silicon body,
• h. selectively depositing a metal layer on the trench.

An MOS transistor integrated with an electrostatic protection structure comprising:

• a. an MOS transistor comprising:
• i. a gate dielectric layer on a gate region of a semiconductor substrate,
• iii. a gate on a portion of the gate dielectric layer,
• iv. a source region and a drain region in the semiconductor substrate adjacent the gate,
• e. a p-n junction diode in the substrate, the p-n junction diode spaced laterally from the MOS transistor,
• f. a trench in the substrate between the MOS transistor and the p-n junction diode, and
• g. a metal layer selectively deposited on the trench.

A device comprising a DMOS transistor integrated with an electrostatic protection structure (ESD) in a common substrate, the substrate comprising a silicon body covered with an epitaxial silicon layer, the epitaxial layer having a first region for the DMOS transistor and designated the DMOS region, a second region for the ESD designated the ESD region, and an isolation space between the DMOS region and the ESD region, the device further comprising:

• a. an MOS gate dielectric layer on the DMOS region,
• b. a polysilicon gate layer on the MOS gate dielectric layer,
• c. a first p-type impurity region in the DMOS region adjacent to the polysilicon gate,
• d. a second p-type impurity region in the ESD region,
• e. a first n-type impurity region adjacent to the polysilicon gate, the first n-type impurity region forming a source for the DMOS transistor,
• f. a second n-type impurity region spaced from the polysilicon gate, the second n-type region forming a drain for the DMOS device,
• g. a third n-type impurity region in the second p-type impurity region of the ESD region, the third n-type impurity region forming with the second p-type impurity region a p-n junction diode,
• h. a lightly doped n-type impurity region between the polysilicon gate and the drain of the DMOS device forming a lightly doped drain (LDD),
• i. a trench extending from the surface of the epitaxial layer to the silicon body,
• j. a metal layer covering the trench.