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US 2003/0169841 A1Published application
High speed digital counters
AssigneeZarlink Semiconductor Inc.
InventorRobertus Laurentius van der Valk
Life of this patent
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Abstract
A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
Claims19
A high speed digital counter comprising a chain of asynchronous counter cells, each asynchronous counter cell comprising:
- a clock input;
- a flip-flop having a master latch and a slave latch;
- and
- a clock gating circuit having a first input connected to said clock input and an enable input connected an output of said master latch.
1 more element
Dependencies are inferred from the claim text.