Semiconductor memory cell configuration and a method for producing the configuration

A method for producing a semiconductor memory cell configuration with bit lines, word lines, and dynamic memory cells that in each case have a trench capacitor and a vertical selection transistor, which comprises:

• forming trench capacitors in a matrix, the trench capacitors and associated ones of the vertical selection transistors of the dynamic memory cells respectively directly following one another in rows and in columns, each trench capacitor having a trench, a block-shaped inner electrode, a dielectric intermediate layer, and an outer electrode, the dielectric intermediate layer being formed in the trench and the inner electrode being subsequently introduced into the trench;
• forming vertical selection transistors substantially above each of the trench capacitors, each vertical selection transistor having a layer sequence disposed offset from the inner electrode of a respective trench capacitor, the layer sequence having a first, upper electrode, an active intermediate layer, and a second, lower electrode, the second, lower electrode being connected to the inner electrode of the respective trench capacitor, and the first, upper electrode being connected to a respective one of the bit lines;
• forming an insulating layer as gate oxide around the active intermediate layer, the insulating layer completely surrounding the intermediate layer;
• depositing a gate electrode layer on the insulating layer and forming a respective one of the word lines from selection transistors along the columns adjacent to the gate electrode layer;
• and
• forming a respective bit line along rows that cross a word line.

A method for producing a semiconductor memory cell configuration with dynamic memory cells that in each case have a trench capacitor and a vertical selection transistor, which comprises:

• forming bit lines and word lines in rows and columns, a respective bit line being formed along rows that cross a word line;
• forming trench capacitors in a matrix, the trench capacitors and associated ones of the vertical selection transistors of the dynamic memory cells respectively directly following one another in rows and in columns, each trench capacitor having a trench, a block-shaped inner electrode, a dielectric intermediate layer, and an outer electrode, the dielectric intermediate layer being formed in the trench and the inner electrode being subsequently introduced into the trench;
• forming vertical selection transistors substantially above each of the trench capacitors, each vertical selection transistor having a layer sequence disposed offset from the inner electrode of a respective trench capacitor, the layer sequence having a first, upper electrode, an active intermediate layer, and a second, lower electrode, the second, lower electrode being connected to the inner electrode of the respective trench capacitor, and the first, upper electrode being connected to a respective one of the bit lines;
• forming an insulating layer as gate oxide around the active intermediate layer, the insulating layer completely surrounding the intermediate layer;
• and
• depositing a gate electrode layer on the insulating layer and forming a respective one of the word lines from selection transistors along the columns adjacent to the gate electrode layer.