US 2003/0166322 A1Published application

Method of manufacturing semiconductor device

AssigneeSeiko Epson Corporation

InventorYoshikazu Kasuya

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Abstract

The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method patterns a stopper layer and a first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on an element separating region in the logic circuit area. The method forms an ONO membrane over the whole surface of the memory area and the logic circuit area, and further forms a second conductive layer above the ONO membrane. The method carries out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area. The method subsequently patterns the first conductive layer in the logic circuit area other than the element separating region to create a gate electrode of an insulated gate field effect transistor in the logic circuit area, and forms a second insulating layer over the whole surface of the memory area and the logic circuit area. This arrangement desirably makes the surface of the polished insulating layer sufficiently flat and even in the subsequent process of polishing the insulating layer.

Claims2

Dependent claims

A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area having a peripheral circuit of the non-volatile memory device, the manufacturing method comprising the steps of:

forming an element separating region on surface of a semiconductor layer to attain insulation between semiconductor elements;
forming a first insulating layer above the semiconductor layer;
forming a first conductive layer above the first insulating layer;
forming a stopper layer above the first conductive layer;
patterning the stopper layer and the first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on the element separating region in the logic circuit area;
forming an ONO membrane over whole surface of the memory area and the logic circuit area;
forming a second conductive layer above the ONO membrane;
carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area;
patterning the first conductive layer in the logic circuit area other than the element separating region to create a gate electrode of an insulated gate field effect transistor in the logic circuit area;
forming a second insulating layer over whole surface of the memory area and the logic circuit area;
and
polishing the second insulating layer to make the stopper layer in the memory area exposed.

9 more elements

forming an element separating region on surface of a semiconductor layer to attain insulation between semiconductor elements;
forming a first insulating layer above the semiconductor layer;
forming a first conductive layer above the first insulating layer;
forming a stopper layer above the first conductive layer;
patterning the stopper layer and the first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on the element separating region in the logic circuit area;
forming an ONO membrane over whole surface of the memory area and the logic circuit area;
forming a second conductive layer above the ONO membrane;
carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area;
removing the stopper layer in the logic circuit area;
patterning the first conductive layer in the logic circuit area to create a gate electrode of an insulated gate field effect transistor in the logic circuit area;
forming side wall insulating layers on both side faces of at least the gate electrode;
forming a first impurity layer as either one of a source area and a drain area of the non-volatile memory device and a second impurity layer as either one of a source area and a drain area of the insulated gate field effect transistor;
forming a silicide layer on surface of the first impurity layer, the second impurity layer, and the gate electrode;
forming a second insulating layer over whole surface of the memory area and the logic circuit area;
polishing the second insulating layer to make the stopper layer in the memory area exposed;
removing the stopper layer in the memory area;
and
patterning the first conductive layer in the memory area, so as to create a word gate of the non-volatile memory device in the memory area.

15 more elements

Dependencies are inferred from the claim text.