Patching methods and apparatus for fabricating memory modules

A method for fabricating a semiconductor memory module on a multi-layer printed circuit board comprising the steps of:

• mounting a plurality of primary memory parts and secondary backup memory parts on said circuit board,
• positioning a lattice type I/O line bit patching network adjacent ones of said primary and said secondary memory parts,
• matching read/write control signal lines for each respective I/O line of one of said primary memory parts with a like I/O line of an individually associated secondary memory part,
• testing each primary and secondary memory part to identify any non-operable I/O lines, and
• patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part by selectively coupling one of said matched read/write control signal lines to said adjacent bit patching network to form a fully operational memory module.

A semiconductor memory module including a plurality of primary memory parts and a plurality of secondary backup memory parts, at least one of said secondary backup memory parts having one or more defective I/O output line segments, said memory module comprising:

• a multi-layer PC board for supporting said primary and secondary memory parts on at least one outer surface thereof,
• a plurality of I/O bit patching networks at least one of which networks is positioned adjacent each memory part,
• a first conductive pathway on said PC board for combining individual memory parts read/write control lines of each primary memory part with an associated backup memory part,
• a second conductive pathway on said PC board for connecting each said individual combined read/write control line to a predetermined conductive tab of a first of said bit patching networks adjacent to a pair of predetermined associated primary memory part and its associated backup secondary memory part, and
• a third conductive pathway for selectively establishing an electrical connection between said first and said second conductive pathways with said bit patching network to operatively replace a non-operable I/O line of a primary memory part with an operable I/O line of said associated backup secondary memory part.