Edge seal for a semiconductor device

An edge seal around the periphery of an integrated circuit device comprising:

• a. a semiconductor substrate;
• b. a layer of dielectric material over the semiconductor substrate, the layer of dielectric material comprising a low-k dielectric material;
• c. a metallic wall of a high conductivity metal in the layer of dielectric material;
• and
• d. a layer of insulation material between the metallic wall and the dielectric material, wherein the insulation material and dielectric material are different materials.

A method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:

• a. providing a semiconductor substrate having a metallic feature therein;
• b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material;
• c. selectively removing a portion of the layer of dielectric material to form two first cavities and expose a portion of the metallic feature;
• d. depositing an insulation material to fill the two first cavities, wherein the insulation material and dielectric material are different materials;
• e. selectively removing a portion of the layer of dielectric material, and any overlying insulation material to form a second cavity;
• f. depositing a barrier metal in the second cavity and on the exposed metallic feature;
• g. depositing a high conductivity metal in the second cavity to fill the cavity;
• and
• h. planarizing the semiconductor substrate down to the layer of dielectric material.

An edge seal around the periphery of an integrated circuit device comprising:

• a. a semiconductor substrate;
• b. a layer of dielectric material over the semiconductor substrate, the layer of dielectric material comprising a low-k dielectric material;
• c. a metallic wall in the layer of dielectric material;
• and
• d. a wall of insulation material between the metallic wall and the periphery of the integrated circuit device wherein the insulation material and dielectric material are different materials.