Gate pad protection structure for power semiconductor device and manufacturing method therefor
AssigneePyramis Corporation
InventorsJun Zeng, Ming-Jiang Zhou, Tzong-Shiann Wu
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Abstract
A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.
Claims14
A method for manufacturing a gate pad protection structure applied in a power semiconductor device, comprising steps of:
- (a) forming a gate oxide layer on a substrate;
- (b) forming a polysilicon layer on said gate oxide layer;
- (c) forming a polysilicon window and a polysilicon window array on said polysilicon layer;
- and
- (d) performing ion implantations via said polysilicon window and said polysilicon window array.
A gate pad protection structure for a power semiconductor device, comprising:
- a substrate;
- a field implantation area disposed in said substrate;
- a field implantation area cell array disposed in said substrate and having plural field implantation area cells each of which substantially has an identical structure to that of said field implantation area, wherein said field implantation area cell array and said field implantation area are simultaneously formed in said substrate;
- and
- a gate pad structure having a polysilicon window and a polysilicon window array formed on said substrate for protecting said gate pad structure by said field implantation area cell array.
Dependencies are inferred from the claim text.