Loading patent…
AssigneeMitsubishi Materials Silicon Corporation
InventorsKazuhiro Ikezawa, Ken Nakajima, Tamiya Karashima, Hiroyuki Shiraki
Estimating the term…
A wafer of the invention is a silicon wafer of 0.02 Ωcm or less in resistivity for deposition of an epitaxial layer, and the number of crystal originated particles (COP) and the number of interstitial-type large dislocation loops (L/D) are respectively 0 to 10 per wafer. A wafer of the invention is an epitaxial wafer having an epitaxial layer being 0.1 Ωcm or more in resistivity and 0.5 to 5 μm in thickness formed on this wafer by means of a CVD method. A wafer of the invention is OSF-free and hardly makes traces of COP and L/D appear on the surface of an epitaxial layer when the epitaxial layer is formed. By heat treatment in a semiconductor device manufacturing process after the epitaxial layer is formed, BMDs occur uniformly and highly in density in the wafer and a uniform IG effect can be obtained in the wafer.
A silicon wafer for deposition of an epitaxial layer, said silicon wafer being 0.02 Ωcm or less in resistivity, wherein the number of crystal originated particles and the number of interstitial-type large dislocation loops are respectively 0 to 10 per silicon wafer.
An epitaxial wafer having a single silicon crystal epitaxial layer being 0.1 Ωcm or more in resistivity and 0.2 to 5 μm in thickness formed on a silicon wafer by means of a chemical vapor deposition method, said silicon wafer being 0.02 Ωcm or less in resistivity, wherein the number of crystal originated particles and the number of interstitial-type large dislocation loops are respectively 0 to 10 per silicon wafer.
An epitaxial wafer comprising
An epitaxial wafer manufacturing method comprising the steps of;
A silicon wafer of 0.02 Ωcm or less in resistivity for deposition of an epitaxial layer, wherein no oxidation induced stacking fault appear in the middle part of said silicon wafer when said wafer is heat-treated in a temperature range of 1000° C.±30° C. for 2 to 5 hours and then successively in a temperature range of 1130° C.±30° C. for 1 to 16 hours in an oxygen atmosphere.
An epitaxial wafer having a single silicon crystal epitaxial layer being 0.1 Ωcm or more in resistivity and 0.2 to 5 μm in thickness formed on a silicon wafer by means of a chemical vapor deposition method, said silicon wafer being 0.02 Ωcm or less in resistivity, wherein no oxidation induced stacking fault appears in the middle part of said wafer when said wafer is heat-treated in a temperature range of 1000° C.±30° C. for 2 to 5 hours and then successively in a temperature range of 1130° C.±30° C. for 1 to 16 hours in an oxygen atmosphere.
An epitaxial wafer manufacturing method comprising the steps of;
Dependencies are inferred from the claim text.