Semiconductor memory device with increased capacitance and reduced preformance fluctuation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorEiji Hasunuma
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Abstract
A semiconductor memory device includes a conductive layer filling a contact hole, a bottom electrode having a depression and electrically connected to the conductive layer, a dielectric film formed on the bottom electrode along the depression, and a top electrode formed on the dielectric film. The conductive layer and the dielectric film directly contact each other at a top surface of the conductive layer. The conductive layer contains polycrystalline silicon and dopant having a relatively low concentration and the bottom electrode contains polycrystalline silicon and dopant having a relatively high concentration. The semiconductor memory device can thus have a capacitor small in size and still sufficiently large in capacitance.
Claims17
A semiconductor memory device comprising:
- a semiconductor substrate having a main surface;
- an interlayer insulation film formed on said main surface of said semiconductor substrate and having a hole reaching said semiconductor substrate;
- a conductive layer filling said hole;
- a bottom electrode having a depression and electrically connected to said conductive layer;
- a dielectric film formed on said bottom electrode along said depression;
- and
- a top electrode formed on said dielectric film, said conductive layer containing silicon and dopant relatively low in concentration, said bottom electrode containing silicon and dopant relatively high in concentration.
A semiconductor memory device comprising:
- a semiconductor substrate having a main surface;
- an interlayer insulation film formed on said main surface of said semiconductor substrate and having a hole reaching said semiconductor substrate;
- a conductive layer filling said hole;
- a bottom electrode having a depression and electrically connected to said conductive layer;
- a dielectric film formed on said bottom electrode along said depression;
- and
- a top electrode formed on said dielectric film, said bottom electrode containing metal.
A semiconductor memory device comprising:
- a semiconductor substrate having a main surface;
- an interlayer insulation film formed on said main surface of said semiconductor substrate and having a hole reaching said semiconductor substrate;
- a conductive layer filling said hole;
- a bottom electrode having a depression and electrically connected to said conductive layer;
- a dielectric film formed on said bottom electrode along said depression;
- and
- a top electrode formed on said dielectric film, said depression being formed by partially removing said bottom electrode with a predetermined etchant, said conductive layer having a relatively low etch rate for said predetermined etchant, said bottom electrode having a relatively high etch rate for said predetermined etchant.
Dependencies are inferred from the claim text.