NMOS ESD protection device with thin silicide and methods for making same
AssigneeTexas Instruments Incorporated
InventorsWei-Tsun Shiau, Craig T. Salling, Jerry Che-Jen Hu
Life of this patent
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Abstract
An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.
Claims24
An NMOS ESD clamping device for protecting an integrated circuit from an ESD event, comprising:
- N type drain and source regions formed in a semiconductor substrate;
- a gate overlying a P-type channel region in the substrate between the source and drain regions;
- a first silicide region formed in one of the drain and source regions of the substrate and having a first thickness;
- and
- a second silicide region formed in the substrate between the gate and the one of the drain and source regions and having a second thickness, wherein the first thickness is greater than the second thickness.
An integrated circuit, comprising:
- a substrate with at least one pad for electrical interconnection of the integrated circuit with another circuit;
- an I/O circuit formed in the substrate and electrically connected to the at least one pad;
- and
- an NMOS ESD clamping device electrically connected to the at least one pad for protecting the I/O circuit from an ESD event, comprising:
- N-type drain and source regions formed in a semiconductor substrate;
- a gate overlying a P-type channel region in the substrate between the source and drain regions;
- a first suicide region formed in one of the drain and source regions of the substrate and having a first thickness;
- and
- a second silicide region formed in the substrate between the gate and the one of the drain and source regions and having a second thickness less than the first thickness.
A method for fabricating an NMOS ESD clamping device on a semiconductor substrate, comprising:
- forming N type drain and source regions separated by a P-type channel region in the substrate;
- forming a gate overlying the P-type channel region region between the source and drain regions;
- forming a first silicide region in one of the drain and source regions of the substrate having a first thickness, and a second silicide region in the substrate between the gate and the one of the drain and source regions having a second thickness less than the first thickness.
Dependencies are inferred from the claim text.