Twin-cell flash memory structure and method
AssigneeInternational Business Machines Corporation
InventorsLouis L. Hsu, Chung H. Lam, Jack A. Mandelman, Carl J. Radens, William R. Tonti
Life of this patent
Estimating the term…
Abstract
A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
Claims19
A pair of programmable memory cells comprising a shared control gate, first and second floating gates having respective gate regions located on respective sides of the control gate, and dielectric structures located between said control gate and respective ones of said gates of said floating gates, wherein said control gate and said gates of said first and second floating gates are located within a space of a single lithographic square.
A pair of programmable memory cells comprising a single control gate, a first floating gate, a second floating gate, a first bitline, and a second bitline, wherein said control gate is self-aligned to said first and second floating gates.
A layout for a non-volatile memory cell comprising a programmable memory cell wordline borderless to a bitline.
Dependencies are inferred from the claim text.