ASIC routing architecture

An integrated circuit, comprising:

• an array of function blocks, wherein each function block has an input and an output;
• a predesigned routing structure formed over the array,
• wherein the predesigned routing structure includes a plurality of conducting layers that include a plurality of pins and a plurality of unbroken conductive paths,
• wherein each pin is in communication with a respective input or output,
• wherein the structure includes a plurality of tracks, and
• wherein in each track is located at least a portion of at least one respective unbroken conductive path and at least one respective pin in one of the plurality of conducting layers, and wherein the unbroken conductive path is uncoupled to the respective pin.

An integrated circuit, comprising:

• an array of function blocks, wherein each function block has an input and an output;
• a predesigned routing structure formed over the array, including:
• a first conducting layer having a plurality of parallel vertical tracks, wherein included in each track is a pin in communication with a respective input or output and in each track is a first portion of an unbroken conductive path, wherein the pin and the first portion are uncoupled to one another;
• for each track, a second portion of the unbroken conductive path, wherein the second portion is formed in at least one other conducting layer.

An integrated circuit, comprising:

• an array of function blocks, to be used in the formation of a user-defined circuit, wherein each function block includes a device layer and at least one device interconnect layer, and wherein each function block has an input and an output;
• a routing structure formed over the array including four conducting layers, wherein:
• a first predesigned conducting layer including a plurality of parallel vertical tracks, wherein each track includes a pin in communication with a respective input or output, and wherein each track includes a first portion of an unbroken conductive path, wherein the pin and the first portion of the unbroken conductive path are uncoupled to one another;
• a second predesigned conducting layer formed under the first conducting layer, wherein for a first group of alternate vertical tracks in the first conducting layer, the second conducting layer includes a second portion of each unbroken conductive path, wherein the second portion is in communication with the respective first portion and is formed substantially under the respective pin,
• a third predesigned conducting layer formed under the second conducting layer, wherein for a second group of alternate vertical tracks in the first conducting layer, the third conducting layer includes a second portion of each unbroken conductive path, wherein the second portion is in communication with the respective first portion and is formed substantially under the respective pin, and
• a customized conducting layer formed over the first predesigned conducting layer and in communication with the first conducting layer, wherein the customized conducting layer has been formed in accordance with a user-defined circuit.

An integrated circuit, comprising:

• an array of function blocks, wherein each function block has an input and an output;
• a predesigned routing structure formed over the array, including:
• a first conducting layer having a plurality of parallel vertical tracks, wherein included in each track is a pin in communication with a respective input or output and in each track is a first portion of an unbroken conductive path, wherein the pin and the first portion are uncoupled to one another;
• for each track, a second portion of the unbroken conductive path, wherein the second portion is formed in at least one other conducting layer;
• a plurality of clock conductors, wherein the clock conductors can be coupled with a customized conducting layer to form multiple independent clock domains.