Apparatus for evaluating lithography process margin simulating layout pattern of semiconductor device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHironobu Taoka, Akihiro Nakae
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Abstract
A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.
Claims6
A lithography process margin evaluating apparatus simulating a light intensity distribution within a photosensitive material on a semiconductor substrate and an actual layout pattern formed on said semiconductor substrate, using a design layout pattern formed on a mask, comprising:
- an analysis condition receiving unit receiving an analysis condition for analyzing said actual layout pattern;
- a layout pattern template holding unit storing a plurality of design layout pattern templates;
- a simulation condition template holding unit storing a plurality of simulation condition templates;
- a measuring condition holding unit storing a plurality of measuring conditions for measuring said actual layout pattern;
- a layout pattern generating unit selecting among said plurality of design layout pattern templates and generating a plurality of design layout patterns based on said analysis condition and said selected design layout pattern template;
- a simulation condition generating unit selecting a simulation condition template and generating a plurality of simulation conditions based on said received analysis condition and said selected simulation condition template;
- a simulation unit simulating the actual layout pattern transferred to the photosensitive material on said semiconductor substrate, using said plurality of design layout patterns and said plurality of simulation conditions;
- a measuring condition determining unit determining a measuring condition among said plurality of measuring conditions, based on said analysis condition;
- and
- a measuring unit measuring said actual layout pattern with said determined measuring condition.
Dependencies are inferred from the claim text.