Self aligned method of forming non-volatile memory cells with flat word line
AssigneeSilicon Storage Technology, Inc.
InventorsPavel Klinger, Sreeni Maheshwarla
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Abstract
A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).
Claims17
A method of making an electrically erasable programmable memory cell, the method comprising the steps of:
- forming a first layer of polysilicon disposed over and insulated from a semiconductor substrate of a first conductivity type;
- forming a block of insulation material over the first polysilicon layer which leaves portions of the first polysilicon layer exposed;
- removing the exposed portions of the first polysilicon layer to form a floating gate underneath the block of insulation material;
- forming a block of polysilicon that is disposed over and insulated from the substrate and is disposed adjacent to and insulated from the floating gate, wherein the formation of the polysilicon block includes a planarization etch for planarizing an upper surface of the polysilicon block using an upper surface of the insulation material block as a planarization etch stop;
- and
- forming spaced apart first and second regions in the substrate that have a second conductivity type, with a channel region defined in the substrate between the first and second regions.
A method of making an array of electrically erasable programmable memory cells, the method comprising the steps of:
- forming a first layer of polysilicon disposed over and insulated from a semiconductor substrate of a first conductivity type;
- forming blocks of insulation material over the first polysilicon layer;
- removing portions of the first polysilicon layer not disposed underneath the blocks of insulation material to form a plurality of spaced apart floating gates;
- forming blocks of polysilicon each disposed over and insulated from the substrate and each disposed adjacent to and insulated from one of the floating gates, wherein the formation of the polysilicon blocks includes a planarization etch for planarizing upper surfaces of the polysilicon blocks using upper surfaces of the insulation material blocks as a planarization etch stop;
- and
- forming spaced apart first and second regions in the substrate that have a second conductivity type, with channel regions each defined in the substrate between one of the first regions and one of the second regions.
Dependencies are inferred from the claim text.