US 2003/0153148 A1 · Method for fabricating a gate structure of a flash memory

Abstract

A method for fabricating a gate of a flash memory is described. A tunneling oxide layer, a first polysilicon layer and a silicon nitride layer are sequentially formed on a substrate. A photo-resist layer is formed on the silicon nitride layer and then the photo-resist layer, the silicon nitride layer, the polysilicon layer, the tunneling oxide layer and the substrate are patterned to form a plurality trenches in the substrate. An active area defined by every two trenches is simultaneously formed. The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the top of the silicon nitride layer. The top portion of the shallow trench isolation structures is removed to expose the sidewall of the silicon nitride layer and the top portion of the sidewall of the first polysilicon layer. Part of the silicon nitride layer is removed by wet etching. Then, a second polysilicon layer is formed on the active area and the shallow trench isolation structures. The second polysilicon layer is etched anisotropically to further expose the top face of the shallow trench isolation structures to form a floating gate. The remaining silicon nitride layer is removed. A conformal dielectric layer is formed over the substrate. A third polysilicon layer is formed on the dielectric layer as a control gate.

Claims30

Dependent claims

A method for fabricating a gate of a flash memory, the method comprising:

providing a substrate;
forming a tunneling oxide layer on the substrate;
forming a first conductive layer on the tunneling oxide layer;
forming a dielectric layer on the first conductive layer;
forming a plurality shallow trench isolation (STI) structures in the substrate, wherein an active area, defined by every two shallow trench isolation structures, is simultaneously formed;
removing a top portion of the shallow trench isolation structures to expose a sidewall of the dielectric layer and portion of a sidewall of the first conductive layer;
a first etching process to remove part of the dielectric layer;
forming a second conductive layer on the active area and the shallow trench isolation structures;
a second etching process to remove the second conductive layer to expose a top face of the shallow trench isolation structures;
removing the dielectric layer;
forming a conformal insulation layer over the substrate;
and
forming a third conductive layer on the dielectric layer.

10 more elements

Dependencies are inferred from the claim text.

Method for fabricating a gate structure of a flash memory

Life of this patent

Method for fabricating a gate structure of a flash memory

Life of this patent

Abstract

Claims30