Semiconductor integrated circuit and method for manufacturing the same

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistors other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor;
• (c) a step of forming an isolation portion by burying an insulation film in said groove after said step (b);
• and
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set the threshold voltage of said second field effect transistor, after said step (c).

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistors other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) a step of forming an isolation portion by burying an insulation film in said groove after said step of forming a groove;
• (c) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor, after said step (b);
• and
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set the threshold voltage of said second field effect transistor, after said step (c).

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a gate insulation film on said semiconductor substrate;
• (b) a step of forming a photoresist pattern on the semiconductor substrate after said step (a) to cover the regions to form said first field effect transistors and to expose other regions, and thereafter removing the gate insulation film exposed by the same used as a mask;
• and
• (c) a step of removing said photoresist pattern after said step (b) and thereafter performing an oxidation process on said semiconductor substrate to form, in the regions to form said first field effect transistors, a gate insulation film thicker than a gate insulation film formed in the region to form said second field effect transistor,
• thereby setting the threshold voltage of at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor.

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor, after said step (a);
• (c) a step of forming an isolation portion by burying an insulation film in said groove after said step of forming a groove after said step (b);
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set the threshold voltage of said second field effect transistor, after said step (c);
• (e) a step of forming a gate insulation film on the semiconductor substrate after said step (d);
• (f) a step of forming a photoresist pattern on the semiconductor substrate after said step (e) to cover the regions to form said first field effect transistors and to expose other regions, and thereafter removing the gate insulation film exposed by the same used as a mask;
• and
• (g) a step of removing said photoresist pattern after said step (f) and thereafter performing an oxidation process on said semiconductor substrate to form, in the regions to form said first field effect transistors, a gate insulation film thicker than a gate insulation film formed in the region to form said second field effect transistor.

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and a second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) a step of forming an isolation portion by burying an insulation film in said groove after said step of forming a groove;
• (c) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor, after said step (b);
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set, the threshold voltage of said second field effect transistor, after said step (b);
• (e) a step of forming a gate insulation film on the semiconductor substrate after said step (d);
• (f) a step of forming a photoresist pattern on the semiconductor substrate after said step (e) to cover the regions to form said first field effect transistors and to expose other regions, and thereafter removing the gate insulation film exposed by the same used as a mask;
• and
• (g) a step of removing said photoresist pattern after said step (f) and thereafter performing an oxidation process on said semiconductor substrate to form, in the regions to form said first field effect transistors, a gate insulation film thicker than a gate insulation film formed in the region to form said second field effect transistor.

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of selectively introducing a first impurity into the region to form said at least one first field effect transistor on said semiconductor substrate;
• and
• (b) a step of selectively introducing nitrogen into the region to form said second field effect transistor on said semiconductor substrate and thereafter forming a gate insulation film on said semiconductor substrate,
• thereby setting the threshold voltage of at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor.

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor, after said step (a);
• (c) a step of forming an isolation portion by burying an insulation film in said groove after said step of forming a groove after said step (b);
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set the threshold voltage of said second field effect transistor, after said step (c);
• and
• (e) a step of selectively introducing nitrogen into the region to form said second field effect transistor on said semiconductor substrate and thereafter forming a gate insulation film on said semiconductor substrate, after said step (d).

A method for manufacturing a semiconductor integrated circuit device having a plurality of first field effect transistors constituting a memory cell of an SRAM and second field effect transistor other than them formed on a semiconductor substrate, which comprising:

• (a) a step of forming a groove on said semiconductor substrate;
• (b) a step of forming an isolation portion by burying an insulation film in said groove after said step of forming a groove;
• (c) an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor, after said step (b);
• (d) an impurity introduction step for selectively introducing a second impurity into a region to form field effect transistors of the same conductivity type on said semiconductor substrate in order to set the threshold voltage of said second field effect transistor, after said step (b);
• and
• (e) a step of selectively introducing nitrogen into the region to form said second field effect transistor on said semiconductor substrate and thereafter forming a gate insulation film on said semiconductor substrate after said step (d).