ESD protection network utilizing precharge bus lines

An integrated circuit comprising:

• functional circuitry;
• a first electrostatic discharge (ESD) bus line to direct electrostatic discharge pulses away from the functional circuitry;
• a first charge pump coupled to charge the first ESD bus line to a predetermined first voltage;
• a second ESD bus line to further direct electrostatic discharge pulses away from the functional circuitry;
• a second charge pump coupled to charge the second ESD bus line to a predetermined second voltage;
• a first unidirectional conducting device coupled between a first signal connection and the first ESD bus line;
• a second unidirectional conducting device coupled between a second signal connection and the second ESD bus line;
• and
• wherein the first and second ESD bus lines are charged to their respective first and second voltage levels to reduce transient currents through the first and second unidirectional conducting devices when voltages applied to the first and second signal connections are outside the normal range of power supply operating voltages for the integrated circuit.

An ESD protected integrated circuit comprising:

• a positive ESD bus line to route positive electrostatic discharge pulses around functional circuitry;
• first and second signal bonding pads to receive external voltage signals;
• a first unidirectional conducting device coupled between the first signal bonding pad and the positive ESD bus line;
• a second bus line coupled to selectively receive current from the positive ESD bus line;
• a second unidirectional conducting device coupled between the second signal bonding pad and the second bus line;
• and
• a positive rail charge pump coupled to charge the positive ESD bus line to a predefined voltage level, wherein the predefined voltage level is higher than anticipated voltage signal levels that will be applied to the first signal bonding pad to reduce parasitic currents through the first unidirectional conducting device during normal operations of the integrated circuit where voltage signals higher than a normal power supply operating voltage, but less than the predefined voltage, are applied to the first signal bonding pad.

An ESD protected integrated circuit comprising:

• a negative ESD bus line to route negative electrostatic discharge pulses around functional circuitry;
• first and second signal bonding pads to receive external voltage signals;
• a first unidirectional conducting device coupled between the first signal bonding pad and the negative ESD bus line;
• a second bus line coupled to selectively receive current from the negative ESD bus line;
• a second unidirectional conducting device coupled between the second signal bonding pad and the second bus line;
• and
• a negative rail charge pump coupled to charge the negative ESD bus line to a predefined voltage level, wherein the predefined voltage level is lower than anticipated voltage signal levels that will be applied to the first signal bonding pad to reduce parasitic currents through the first unidirectional conducting devices during normal operations of the integrated circuit where voltage signals lower than a normal power supply operating voltage, but more than the predefined voltage, are applied to the first signal bonding pad.

A method of operating an integrated circuit having electrostatic discharge protection comprising:

• coupling a positive ESD bus line to the integrated circuit to direct positive electrostatic pulses away from functional circuitry of the integrate circuit;
• pre-charging the positive ESD bus line to a predetermined positive voltage level, wherein the predetermined positive voltage level is above a voltage level of expected signals to be applied to the integrated circuit;
• coupling a negative ESD bus line to the integrated circuit to direct negative electrostatic pulses away from the functional circuitry of the integrated circuit;
• and
• pre-charging the negative ESD bus line to a predetermined negative voltage level, wherein the predetermined negative voltage level is below the voltage level of expected signals to be applied to the integrated circuit.