US 2003/0151865 A1 · Electrostatic discharge protection circuit

Abstract

Provided is an electrostatic discharge protection circuit for protecting from electrostatic destruction an Integrated Circuit (IC) formed from a CMOS material that is capable of handling high frequencies and can withstand low voltage. The electrostatic discharge protection circuit has NMOS transistors, which are diode-connected transistors oriented in opposite directions, connected in parallel between a ground line and a line connecting an input terminal of the IC and the gate of an NMOS transistor included in an amplifier. The electrostatic discharge protection circuit is highly resistive to a surge voltage without impairment by high-frequency characteristics including noise and signal loss. The size of the IC need not be significantly increased to incorporate the new electrostatic discharge protection circuit, which is also highly cost effective since it requires fewer manufacturing steps to produce.

Claims20

Dependent claims

An electrostatic discharge protection circuit comprising:

a line connecting a pad of an integrated circuit and an input terminal of an internal amplifier;
and
first and second diode connections, having a plurality of diodes, connected in parallel between said line and a ground line.

Dependencies are inferred from the claim text.

Electrostatic discharge protection circuit

Life of this patent

Electrostatic discharge protection circuit

Life of this patent

Abstract

Claims20