Method of forming a vertical double gate semiconductor device and structure thereof

A method of forming a vertical double gate semiconductor device comprising:

• providing a semiconductor substrate;
• forming a first insulating layer over the semiconductor substrate;
• forming a first semiconductor layer on the first insulating layer;
• etching portions of the first semiconductor layer to form a semiconductor structure having a first sidewall and a second sidewall, wherein the first sidewall is opposite the second sidewall in a first direction;
• forming a source region and a drain region in the semiconductor substrate in a second direction, wherein the first direction is substantially perpendicular the second direction;
• forming a second insulating layer on the first sidewall and the second sidewall;
• forming a second semiconductor layer over the semiconductor structure and the second insulating layer, wherein the second semiconductor layer comprises:
• a first semiconductor portion which is adjacent the first sidewall;
• a second semiconductor portion which is over the semiconductor structure;
• and
• a third semiconductor portion which is adjacent the second sidewall;
• doping the first semiconductor portion and the third semiconductor portion;
• and
• removing the second semiconductor portion.

A vertical double gate semiconductor device comprising:

• a semiconductor substrate;
• a first insulating layer over the semiconductor substrate;
• a semiconductor structure over the first insulating layer having a first current electrode region, a second current electrode region, a first sidewall and a second sidewall, wherein:
• the first current electrode region and the second current electrode region are separated by a channel region in a first direction;
• and
• the first sidewall and the second sidewall are opposite each other in a second direction, wherein the first direction is substantially perpendicular to the second direction;
• a first control electrode region over the first sidewall;
• and
• a second control electrode region over the second sidewall, wherein the first control electrode region and second control electrode region are not contiguous portions of a same material.