Semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorShigeru Ishibashi
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Abstract
A semiconductor memory includes a silicon substrate having a cell array region wherein plural rectangular silicon pillars are formed in rows and columns by a trench having a width of la and formed in a lattice form, a storage node formed on at least a surface of a lower portion of the silicon pillar, a well region formed in an upper half above the storage node, a diffusion layer formed on an upper surface of the well region, a capacitor dielectric formed on the storage node to surround the lower portion of the silicon pillar, a plate electrode buried in the lower portion of the trench to substantially the same level as the upper end of the storage node, and a first gate electrode formed on the channel portion via a first gate insulator.
Claims20
A semiconductor memory comprising:
- a first-conductivity-type silicon substrate having a cell array region in which a plurality of rectangular silicon pillars are formed in rows and columns by a trench having a width of 1a and formed in a form of a lattice, lengths of adjacent sides of each of the silicon pillars being 1a and 1b;
- a storage node formed of a second-conductivity-type semiconductor layer on at least a surface of a lower portion of each of the plurality of silicon pillars;
- a first-conductivity-type well region formed in an upper half above the storage node of each of the plurality of silicon pillars, a portion of the well region present on one side surface of each of the silicon pillars functioning as a channel portion of a vertical MIS transistor;
- a second-conductivity-type diffusion layer formed on an upper surface of the well region;
- a capacitor insulating film formed on the storage node so as to surround the lower portion of each of the plurality of silicon pillars;
- a plate electrode buried in a lower portion of the trench to substantially the same level as an upper end of the storage node;
- a first gate insulating film of the vertical MIS transistor formed on a surface of the channel portion;
- and
- a first gate electrode formed on the first gate insulating film so as to oppose the channel portion.
A semiconductor memory comprising:
- a first-conductivity-type silicon substrate having a cell array region in which a plurality of rectangular silicon pillars are formed in rows and columns by a trench having a width of 1a and formed in a form of a lattice, lengths of adjacent sides of each of the silicon pillars being 1a and 1b;
- a storage node formed of a second-conductivity-type semiconductor layer on at least a surface of a lower portion of each of the plurality of silicon pillars;
- a first-conductivity-type well region formed in an upper half above the storage node of each of the plurality of silicon pillars, a portion of the well region present on one side surface of each of the silicon pillar functioning as a channel portion of a vertical MIS transistor;
- a second-conductivity-type diffusion layer formed on an upper surface of the well region;
- a capacitor insulating film formed on the storage node so as to surround the lower portion of each of the plurality of silicon pillars;
- a plate electrode buried in a lower portion of the trench to substantially the same level as an upper end of the storage node;
- a first gate insulating film of the vertical MIS transistor formed on a surface of the channel portion;
- and
- a first gate electrode formed of a metal on the first gate insulating film so as to oppose the channel portion.
Dependencies are inferred from the claim text.