Method using wet etching to trim a critical dimension
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Huan Tsai, Ming-Jie Huang, Huan-Just Lin, Hun-Jan Tao
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Abstract
A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.
Claims20
A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control comprising the steps of:
- providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process;
- isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process;
- and
- anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.
A method for forming a semiconductor feature on a semiconductor wafer comprising the steps of:
- providing a semiconductor wafer including multiple layers comprising at least one metal nitride layer overlying a polysilicon containing layer;
- photolithographically patterning the metal nitride layer to form a patterned etching surface;
- anisotropically plasma etching through a thickness of the patterned etching surface to reveal a first exposed portion of the polysilicon containing layer according to a plasma etching process;
- etching according to a wet etching process to reduce a width portion of the at least one metal nitride layer to reveal a second exposed portion of the polysilicon containing layer;
- and
- anisotropically plasma etching through the second exposed portion of the polysilicon layer to form a semiconductor feature.
Dependencies are inferred from the claim text.