Poly-silicon thin film transistor having back bias effects and fabrication method thereof
AssigneeNeopoly Inc.
InventorsSeung Ki Joo, Ki Bum Kim, Yeo Geon Yoon
Life of this patent
Estimating the term…
Abstract
A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.
Claims15
A method of fabricating a poly-silicon (poly-Si) thin film transistor (TFT) having back bias effects, the poly-Si TFT fabrication method comprising the steps of:
- (a) forming a conducting underlayer to which a back bias voltage is applied by using a conductive material on the entire surface of one side of a glass substrate;
- (b) forming a buffer layer by using an insulation material on the upper portion of the conducting underlayer;
- and
- (c) forming a poly-Si TFT on the upper portion of the buffer layer.
A poly-silicon (poly-Si) thin film transistor (TFT) having back bias effects, the poly-Si TFT comprising:
- a glass substrate;
- a conducting underlayer formed of a conductive material on the entire surface of one side of the glass substrate where the back bias voltage is applied;
- a buffer layer formed of an insulation material on the upper portion of the conducting underlayer;
- and
- a poly-Si TFT formed on the upper portion of the buffer layer.
A poly-Si TFT having back bias effects, the poly-Si TFT comprising:
- a glass substrate;
- an island type buried electrode pad formed of a conductive material on one side of the glass substrate where the back bias voltage is applied;
- a buffer layer formed of an insulation material on the entire surface of the glass substrate;
- and
- a poly-Si TFT formed on the upper portion of the buffer layer.
A double gate type TFT comprising:
- a glass substrate;
- a buried type lower gate pad for applying a back bias voltage on one side of the glass substrate;
- a buffer layer formed of an insulation material on the entire surface of the glass substrate;
- an active region formed of a poly-Si TFT on the upper portion of the buffer layer;
- source and drain regions which are formed on both sides of the active region, respectively;
- a gate oxide film formed on the upper portion of the channel region between the source and drain regions;
- and
- an upper gate formed on the upper portion of the gate oxide film,
- wherein an identical gate voltage is applied to both the upper gate and the buried type lower gate pad.
Dependencies are inferred from the claim text.