Method for patterning semiconductors through adjustment of image peak side lobes

A method for patterning the semiconductor devices, the method comprising:

• providing a first exposure peak of a main feature that is utilized for the lithography process, wherein a side-lobe is beside on the sidewall of said first exposure peak, and said first exposure peak has a first pitch;
• performing an adjusting step to change a first optical parameter and a second optical parameter, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof;
• and
• performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch.

A method for reducing the pitch of the semiconductor devices, the method comprising:

• providing a semiconductor substrate with a semiconductor layer thereon;
• forming a photoresist layer on said semiconductor layer;
• providing a first exposure peak of a main feature with a first width that is utilized for the lithography process, wherein a plurality of side-lobes are individually beside on the sidewalls of said first exposure peak, and said first exposure peak has a first pitch;
• adjusting a first optical parameter of Numerical Aperture (NA) and a second optical parameter of sigma, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof;
• performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch, so as to form a plurality of photoresist regions on said semiconductor layer, wherein said halftone mask equalizes the intensity of said plurality of exposure peaks from each other, and said second pitch is half said first pitch;
• and
• performing an etching process by using said plurality of photoresist regions as photoresist masks to etch said semiconductor layer, so as to form a plurality of semiconductor regions with a second width.