Mask alignment method
AssigneeInfineon Technologies North America Corp.
InventorsEnio L. Carpi, Bernhard Liegl, Peter Thwaite
Life of this patent
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Abstract
Disclosed is a method of aligning a mask with a semiconductor wafer surface, comprising the steps of providing a semiconductor surface with one or more wafer alignment marks thereon, providing a mask with one or more etchings effective in generating one or more 0-π-phase-conflict alignment marks under ambient lighting conditions of use, wherein each said wafer alignment mark is of a geometry that is compatibly aligning with a corresponding 0-π-phase-conflict alignment mark, and aligning said 0-π-phase-conflict alignment marks with their corresponding wafer alignment marks.
Claims13
A method of aligning a mask with a semiconductor wafer surface, comprising the steps of:
- providing a semiconductor surface with one or more wafer alignment marks thereon;
- providing a mask with one or more etchings effective in generating one or more 0-π-phase-conflict alignment marks under ambient lighting conditions of use;
- wherein each said wafer alignment mark is of a geometry that is compatibly aligning with a corresponding 0-π-phase-conflict alignment mark;
- and
- aligning said 0-π-phase-conflict alignment marks with their corresponding wafer alignment marks.
A 0-π-phase conflict mask, comprising:
- a mask comprising a transparent base material, having at least one depression etched thereon, said depression effective in generating a 0-π-phase-conflict mark under ambient lighting conditions of use.
A method of making a semiconductor manufacturing mask, comprising the steps of:
- providing a transparent base material;
- providing said base material with an attenuating layer;
- patterning said attenuating layer with a resist layer, said resist layer patterned to expose a portion of said base material;
- and
- etching, at said exposed portion, a depression to a depth effective in generating a 0-π-phase-conflict mark under ambient lighting conditions of use, said mark positioned to align with a corresponding mark on a semiconductor wafer.
Dependencies are inferred from the claim text.