Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method

A method of designing a semiconductor circuit for a semiconductor device including a first interconnection layer having relatively short line length, a first insulator formed to surround said first interconnection layer, a second interconnection layer having long line length than said first interconnection layer and a second insulator formed to surround said second interconnection layer, comprising the steps of:

• preparing a first interconnection structure pattern including a plurality of interconnection layers having a prescribed space between lines and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material;
• preparing a second interconnection structure pattern including a plurality of interconnection layers having a distance between lines approximately the same as said distance between lines and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material;
• calculating a first parasitic capacitance of each interconnection layer of said first interconnection structure pattern;
• calculating a second parasitic capacitance of each interconnection layer of said second interconnection structure pattern;
• selecting the material of said interconnection layer of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first interconnection layer;
• and
• selecting the material of said insulator of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first insulator.

A semiconductor device, comprising:

• an interconnection layer having one side surface and the other side surface positioned opposite to said one side surface;
• and
• a barrier metal layer formed on said one side surface and said the other side surface;
• wherein
• total film thickness BM of said barrier metal layer is selected to satisfy the relation of
• BMmin/W≦BM/W≦1−(K/(K−1))×ΔW/W
• where W represents set line width of said interconnection layer in a direction approximately vertical to said one side surface,
• BM represents total film thickness of said barrier metal layer formed on said one side surface and said the other side surface,
• BMmin represents minimum necessary film thickness of said barrier metal layer, and
• K represents tolerable ratio of increase in resistance of said interconnection layer when said set line width W is reduced by ΔW.