SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection
AssigneeIndustrial Technology Research Institute
InventorsMing-Dou Ker, Kei-Kang Hung, Chyh-Yih Chang
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Abstract
A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.
Claims35
An integrated circuit device, comprising:
- a semiconductor substrate;
- an isolation layer formed over the semiconductor substrate;
- and
- a layer of silicon material, formed over the isolation layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, a second n-type portion contiguous with the second p-type portion, a third p-type portion contiguous with the second n-type portion, and a third n-type portion contiguous with the third p-type portion,
- wherein the first, second, and third p-type portions and the first, second, and third n-type portions collectively form a rectifier,
- wherein the first p-type portion and the first n-type portion form a cathode of the rectifier, and
- wherein the third n-type portion and the third p-type portion form an anode of the rectifier.
An integrated circuit device, comprising:
- a semiconductor substrate;
- an isolation layer formed over the semiconductor substrate;
- an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer;
- and
- a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a rectifier to provide electrostatic discharge protection.
A method for protecting a silicon-on-insulator semiconductor circuit from electrostatic discharge, comprising:
- providing an n-type MOS transistor having a source region and a drain region in the silicon-on-insulator circuit;
- providing a p-type MOS transistor having a source region and a drain region, the p-type MOS transistor being contiguous with the n-type MOS transistor;
- providing a p-type region contiguous with one of the source region and the drain region of the n-type MOS transistor to form a cathode;
- and
- providing an n-type region contiguous with one of the source region and the drain region of the p-type MOS transistor to form an anode, wherein the n-type region, the p-type region, the p-type MOS transistor and the n-type MOS transistor form a rectifier.
Dependencies are inferred from the claim text.